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32174 Datasheet(PDF) 30 Page - Renesas Technology Corp |
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32174 Datasheet(HTML) 30 Page - Renesas Technology Corp |
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30 / 881 page ![]() 1 1-7 32170/32174 Group User's Manual (Rev. 2.1) OVERVIEW 1.2 Block Diagram 1.2 Block Diagram Figure 1.2.1 shows a block diagram of the 32170/32174. Features of each block are shown in Tables 1.2.1 through 1.2.3. Figure 1.2.1 Block Diagram of the 32170/32174 PLL clock generator circuit Internal bus interface Address Data Internal RAM (M32170F6:40KB) (M32170F4:32KB) (M32170F3:32KB) (M32174F4:40KB) (M32174F3:40KB) Internal flash memory (M32170F6:768KB) (M32170F4:512KB) (M32170F3:384KB) (M32174F4:512KB) (M32174F3:384KB) M32R CPU core (max 40MHz) Multiplier- accumulator (32 × 16 + 56) DMAC (10 channels) Multijunction timer (MJT: 64 channels) Serial I/O (6 channels) A-D converter (10-bit resolution, 16 channels) × 2 Wait controller Interrupt controller (31 sources, 8 levels) Real-time debugger (RTD) External bus interface Input/output port (JTAG), 157 lines Full CAN (1 channel) 32170/32174 |
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