32174 datasheet(74/881 Pages) RENESAS

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3-13

32170/32174 Group User's Manual (Rev. 2.1)

ADDRESS SPACE

3.4 Internal ROM/SFR Area

Figure 3.4.4 Outline Address Mapping of the SFR Area

H’0080 0000

H’0080 007E

H’0080 0180

Interrupt

controller (ICU)

H’0080 0080

A-D0 converter

H’0080 00EE

Serial I/O0-3

H’0080 0100

H’0080 0146

Wait controller

MJT (common part)

MJT (TOP)

MJT (TIO)

MJT (TMS)

H’0080 0200

H’0080 0240

H’0080 0300

H’0080 03C0

H’0080 03E0

H’0080 03FE

Note: The Real-time Debugger (RTD) is designed to be an independent module

operated from an external source, and is transparent to the CPU.

7 8

H’0080 0A00

+0 address

+1 address

7 8

Multijunction timer

(MJT)

Flash control

H’0080 07E0

H’0080 07F2

H’0080 023E

H’0080 02FE

MJT (TOD0)

H’0080 078C

H’0080 07DE

MJT (TID0)

H’0080 0790

H’0080 078E

Multijunction timer

(MJT)

Serial I/O4, 5

H’0080 0A26

H’0080 0A80

A-D1 converter

H’0080 0AEE

MJT (TOD1)

MJT (TOM0)

H’0080 0BDE

H’0080 0C8C

H’0080 0CDE

MJT (TML1)

H’0080 0FE0

H’0080 0FFE

H’0080 0400

DMAC

H’0080 0478

CAN0

H’0080 1000

H’0080 11FE

H’0080 0700

Input/output port

H’0080 0756

H’0080 03BE

H’0080 03D8

MJT (TML0)

H’0080 0B8C

MJT (TID1)

H’0080 0B8E

H’0080 0B90

H’0080 0C8E

H’0080 0C90

MJT (TID2)

H’0080 0760

H’0080 3FFE

+0 address

+1 address

Multijunction timer

(MJT)

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