32174 datasheet(25/881 Pages) RENESAS

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1-2

32170/32174 Group User's Manual (Rev. 2.1)

1.1 Outline

1.1.1 M32R Family CPU Core

(1) Based on RISC architecture

• The 32170 and 32174 are 32-bit RISC single-chip microcomputers; each of them is built

around the M32R family CPU core (hereafter referred to as the M32R) and incorporates flash

memory, RAM, and various other peripheral functions-all integrated into a single chip.

• The M32R is based on RISC architecture. Memory access is performed using load and store

instructions, and various arithmetic operations are executed using register-to-register

operation instructions. The M32R internally contains sixteen 32-bit general-purpose registers

and has 83 distinct instructions.

• The M32R supports compound instructions such as Load & Address Update and Store &

Address Update, in addition to ordinary load and store instructions. These compound

instructions help to speed up data transfers.

(2) 5-stage pipelined processing

• The M32R uses 5-stage pipelined instruction processing consisting of Instruction Fetch,

Decode, Execute, Memory Access, and Write Back. Not just load and store instructions or

Update and Store & Address Update also are executed in one cycle.

• Instructions are entered into the execution stage in the order they are fetched, but this does not

always mean that the first instruction entered is executed first. If the execution of a load or

store instruction entered earlier is delayed by one or more wait cycles inserted in memory

access, a register-to-register operation instruction entered later may be executed before said

load or store instruction. By using "out-of-order-completion" like this, the M32R controls

instruction execution without wasting clock cycles.

(3) Compact instruction code

• The M32R instructions come in two types: one consisting of 16 bits in length, and the other

consisting of 32 bits in length. Use of the 16-bit length instruction format especially helps to

suppress the program code size.

• Some 32-bit long instructions can branch directly to a location 32 Mbytes forward or backward

from the instruction address being executed. Compared to architectures where address space

is segmented, this direct jump allows for easy programming.

OVERVIEW

1.1 Outline

32174 Datasheet(PDF) 25 Page - Renesas Technology Corp