AD7280 datasheet(6/33 Pages) AD

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AD7280

Preliminary Technical Data

Rev. PrD | Page 6 of 33

PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS

48 47 46 45 44 43 42

41 40 39

38 37

VT4

VT5

VT6

AVCC

AGND

VTTERM

VT3

VDRIVE

ALERTlo

ALERT

SDOlo

SDO

CB6

VIN5

CB5

VIN3

CB4

VIN4

VIN6

CB3

VIN2

CB2

CB1

VIN1

13 14 15 16 17 18 19 20 21 22 23 24

PIN 1

AD7280

TOP VIEW

Figure 2.

VIN6

CB6

VIN5

CB5

VIN4

CB4

VIN3

CB3

VIN2

CB2

VIN1

CB1

VT4

VT5

VT6

VTTERM

AGND

AVCC

VDRIVE

ALERTlo

ALERT

SDO

SDOlo

VT3

TOP VIEW

PIN 1

INDICATOR

AD7280

Figure 3.

Table 4.

Pin No.

Mnemonic

Description

1, 3, 5, 7,

9, 11, 13

Vin6 to

Vin0

Analog Input 0 to Analog Input 6. Analog input 0 should be connected to the base of the series connected

battery cells. Analog Input 1 should be connected to the top of cell 1, Analog Input 2 should be connected to

the top of cell 2, etc. The Analog Inputs are multiplexed into the on-chip track-and-hold allowing the potential

across each cell to be measured.

2, 4, 6, 8,

10, 12

CB6 to CB1

Cell Balance Outputs. These provide a voltage output which can be used to supply the gate drives of a cell

balancing transistor network. Each CB(n) output provides a 5V voltage output referenced to the absolute

voltage of Cell(n-1).

MASTER

Voltage Input. In an application with 2 or more AD7280s Daisy Chained the MASTER pin of the AD7280

connected directly to the DSP or uP should be connected to the VDD supply pin through a 10kOhm resistor. The

MASTER pin on the remaining AD7280s in the application should be tied to their respective VSS supply pins

through 10kOhm resistors.

Power down Input. This input is used to power down the AD7280. When acting as master the PD input is

supplied from the DSP/uP. When acting as a slave on the Daisy Chain the PD input should be connected to the

PDhi output of the AD7280 immediately below it in potential in the Daisy Chain. This input can also be tied to

VCC and the power down initiated through the serial interface.

VDD

Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure

AD7280. The supply must be greater than a minimum voltage of 7.5 V. In an application monitoring the cell

voltages of up to 6 series connected battery cells the supply voltage may be supplied directly from the cell with

the highest potential. The maximum voltage which can be applied between VDD and VSS is 30V. Place 10 µF and

100 nF decoupling capacitors on the VDD pin.

VSS

Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure

of the AD7280. This input should be at the same potential as the AGND voltage.

VREG

Analog Voltage output, 5V. The internally generated VREG voltage, which provides the supply voltage for the

ADC core, is available on this pin for use external to the AD7280. Place 10 µF and 100 nF decoupling capacitors

on the VREG pin.

DVCC

Digital Supply Voltage, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential.

For best performance, it is recommended that the DVCC and AVCC pins be shorted together, to ensure that the

voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled

to DGND. Place 100 nF decoupling capacitors on the DVCC pin. The DVCC supply pin should be connected to the

VREG output

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