AD7280 datasheet(25/33 Pages) AD

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Preliminary Technical Data

AD7280

Rev. PrD | Page 25 of 33

SERIAL INTERFACE

The AD7280’s serial interface consists of four signals; CS, SCLK,

SDIN and SDOUT. The SDIN line is used for transferring data

into the on chip registers while the SDOUT line is used for

reading the conversion results from the ADCs. SCLK is the

serial clock input for the device, and all data transfers, either on

SDIN or on SDOUT, take place with respect to SCLK. Data is

clocked into and out of the AD7280 on the SCLK falling edge.

The CS, input is used to frame the serial data being transferred

to or from the device. CS, can also be used to initiate the

sequence of conversions.

In a Li-Ion Battery Monitoring application up to50 AD7280’s

may be daisy chained together to allow up to 300 individual Li-

Ion cell voltages to be monitored. Each write operation must

therefore include Device Address and Register Address in

addition to the data to be written. An additional identifier bit is

also required when addressing all AD7280s in the Daisy Chain.

The AD7280 SPI Interface, in combination with the Daisy

Chain Interface, allows any register in the 50 x AD7280 stack to

be updated using one 24-bit write cycle.

Table 30. 24-Bit Write Cycle

Device

Address1

Address

Data

Address

All Parts

Additional

Zero’s

D23-D18

D17-D12

D11- D4

D2-D0

There are two different types of read operation for the AD7280.

•

Conversion Results Read

1 Device Address should be written LSB first. For example, to address device

#1 the sequence of bits input to the AD7280 should be 100000. The Register

Address and Data bits are input MSB first.

•

The data returned from a conversion result read operation

includes the Device Address and Channel Address information

in addition to the 12-bits of conversion data. The data returned

from a Register Data read operation includes the Device

Address and Register Address in addition to the 8-bits of

the Daisy Chain Interface, allows the conversion results of any

AD7280 in the 50 x AD7280 stack to be read back using an N x

24-bit read cycle, where N is defined by the number of

conversions completed on that part, that is 12, 9 or 6 (Please

refer to Table 6). The user has the option of taking CS low for

the duration of the N x 24 bit read cycle, or may pulse CS low

for each individual 24-bit read cycle, that is N 24-bit wide CS

frames.

Table 31. 24-Bit Read Conversion result Cycle

Device

Address2

Channel

Address

Conversion

Data

2bit CRC

D23-D18

D17-D14

D13-D2

D1-D0

Table 32. 24-Bit Read Register Data Cycle

Device

Address2

Address

Data

Zero

2-bit

CRC

D23-D18

D17-D12

D11-D4

D3-D2

D1-D0

Figure 20 shows the timing diagram for the serial interface of

the AD7280. Please refer to the Daisy Chain Interface section

for further information on the Daisy Chain Interface.

2 Device Address is read out LSB first. The Register Address, Channel Address

and all Data bits are read out MSB first.

SDO

THREE-

STATE

THREE-STATE

SCLK

424

MSB-1

MSB

LSB

t11

SDI

MSB

MSB-1

LSB

t10

Figure 20. Serial Interface Timing Diagram

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