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AD7280

Preliminary Technical Data

Rev. PrD | Page 14 of 33

REFERENCE

The internal reference is temperature compensated to 2.5 V ± 5

mV. The reference is trimmed to provide a typical drift of

3 ppm/°C . The internal reference circuitry consists of a 1.2 V

band gap reference and a reference buffer. The AD7280 internal

reference is available at the VREF pin. The VREF pin should be

decoupled to AGND using a 10 µF, or greater, ceramic

capacitor. The CREF pin should be decoupled to AGND using a

0.1 µF, or greater, ceramic capacitor. The internal reference is

capable of driving an external load of up to 10kOhms.

CONVERTING CELL VOLTAGES AND

TEMPERATURES

A conversion may be initiated on the AD7280 using either the

CNVST input or the serial interface. A single CNVST signal is

required to initiate conversions on all 12 channels, that is 6

voltage and 6 temperature channels. Alternatively the

conversion can be initiated through the rising edge of CS on the

SPI interface.

When using the CNVST input the falling edge of CNVST places

the track and hold on the voltage inputs Vin0 and Vin1, that is

across Cell 1, into hold mode and initiates the conversion. At

the end of the first conversion the AD7280 generates an internal

End of Conversion signal. This internal EOC will select the

next cell voltage inputs for measurement though the

multiplexer, that is Vin1 and Vin2. The track-and-hold circuit

will acquire the new input voltage and a second internal convert

start signal is generated which places the track-and-hold into

hold mode and initiates the conversion. This process is repeated

until all the selected voltage and temperature cell inputs have

been converted. Please refer to Figure 12 and Figure 13. Note,

once all selected conversions have been completed voltage

inputs Vin0 and Vin1 are again selected through the multiplexer

and the voltage across Cell 1 is acquired in preparation for the

next conversion request.

By setting bits D15 and D14 in the control register the voltage

and temperature cells to be converted are selected. There are

four options available.

Table 6. Voltage and Temperature Cell Selection

D15 to

D14

Voltage inputs

Temperature

Inputs

1 to 6

1, 3 & 5

1 to 6

None

ADC Self Test

None

Each voltage and temperature conversion requires a minimum

of 1us to acquire and convert the cell voltage or temperature

voltage input. For example. when D15 and D14 are set to zero

the falling edge of CNVST will trigger a series of 12

conversions. This will require a minimum of 12µs to convert all

selected measurements. If no temperature conversions are

required then Bits D15 and D14 would be set to 10. In this case

the conversion request will trigger a series of 6 conversions,

requiring a minimum of 6µs.

Track-and-Hold

The track-and-hold on the analog input of the AD7280 allows the

ADC to accurately convert an input sine wave of full-scale

amplitude to 12-bit accuracy.

Following a completed conversion the AD7280 enters its

tracking mode. The time required to acquire an input signal

depends on how quickly the sampling capacitor is charged. This

in turn will depend on the input impedance and any external

components placed on the analog inputs. The default acquisition

time of the AD7280 on initial power up is 400 ns. This can be

increased in steps of 400ns to 1.6 us to provide flexibility in

selecting external components on the analog inputs. The

acquisition time is selected by writing to bits D6 and D5 in the

CONTROL register.

Table 7.Analog Input Acquisition Time.

D6 to D5

Acquisition Time

400 ns

800 ns

1.2

µs

1.6

µs

The acquisition time required is calculated using the following

formula:

tACQ = 10 × ((RSOURCE + R) C)

where:

C is the sampling capacitance, the value of the sampling

capacitor, 18pF

R is the resistance seen by the track-and-hold amplifier looking

at the input, 500Ω.

RSOURCE should include any extra source impedance on the

analog input.

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