AD7280 datasheet(28/33 Pages) AD

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AD7280

Preliminary Technical Data

Rev. PrD | Page 28 of 33

DAISY CHAIN INTERFACE

In a Li-Ion Battery Monitoring application up to 50 AD7280’s

may be daisy chained together to allow up to 300 individual Li-

Ion cell voltages to be monitored. Each AD7280 is capable of

monitoring up to 6 Li-Ion cells and is powered from the top and

bottom voltage of the 6 Li-Ion cells. As a result the supply

voltages of each AD7280 are offset by up to 30V from adjacent

AD7280’s in the chain. For this reason a standard Serial

Interface Daisy Chain method cannot be used.

The AD7280 includes a Daisy Chain Interface separate to the

standard SPI interface. This Daisy Chain interface allows each

AD7280 in the chain to relay data to and from adjacent

AD7280’s. In addition to the standard wire SPI the AD7280

serial interface include 3 optional interface pins, ALERT,

CNVST and PD.

Each input and output pin on the 7 wire interface requires at

least one additional I/O for the Daisy Chain Interface, that is to

allow the information to passed to an AD7280 operating at a

higher supply voltage. The SDO and ALERT outputs will also

require a further daisy chain pin to allow the information to be

passed to an AD7280 operating at a lower supply voltage. The

remaining 5 interface pins, CS, SCLK, SDI, CNVST and PD do

not require additional pins to pass information to a AD7280

operating at a lower voltage as each of these input pins can

operate as both SPI inputs or Daisy Chain inputs. Their

functionality is defined by the state of the Master pin.

The MASTER pin on the AD7280 at the base of the Daisy

Chain should be set high, tied to VDD supply, to ensure that this

device interfaces to the DSP or µProcessor using the standard

Serial Interface. The MASTER pin on the remaining AD7280s

in the Daisy Chain should each be connected to their respective

VSS pins which disables the serial interface pins on those

devices. This allows the CS, SCLK, SDI, CNVST and PD inputs,

in addition to the SDOlo and ALERTlo outputs, to pass signals

to and from an AD7280 operating at a lower potential.

As explained in the Serial Interface section only one 24-bit write

cycle is required to write to any register in the 50 x AD7280

stack . To read back the conversion data from all channels

monitoring the battery stack requires only a (24 x N)-bit read

cycle where N is the number of channels in the battery stack.

Note: this is the default read configuration on power up. If the

settings of the Read or control registers have been changed then

additional write cycles may be required. The recommended

SCLK frequency to ensure correct operation of the Daisy Chain

Interface is 1MHz. With a 1MHz SCLK it will take ~2.34 ms to

read back the voltage conversions on 96 channels.

Addressing the AD7280

As explained in the previous section all write operations to the

AD7280 must include the Device Address and Register Address

in addition to the data to be written. In any application using a

chain of AD7280’s the Device Address corresponds to the

position of the individual AD7280 in the chain with respect to

the device acting as Daisy Chain Master, that is the device

connected directly to the DSP/µP. For example, in an

application which uses 16 AD7280’s to monitor 96 channels the

device acting as Daisy Chain Master should be addressed with a

Device Address of 00000, the 16th AD7280 in the chain should

be addressed with a Device Address of 001111.

Each individual AD7280 is preset with an address of zero, that

is, 0h. When a write operation is initiated by the DSP or

Processor the Daisy Chain Master compares the Device

Address received with its own address. If the addresses do not

match the AD7280 will decrement the Device Address by one,

1h, and the new Device Address will be passed to the next

AD7280 in the chain with the remainder of the original 24-bit

write. The second AD7280 will again compare the received

Device Address with its own address, if the addresses do not

match 1h will be subtracted from the Devices Address and

again passed up the chain. This will continue until the received

Device Address matches the preset address, 0h, and the write

operation is completed.

The same principle will apply when transferring data down the

stack to the DSP or µProcessor. The Device Address supplied

from each individual AD7280 will be incremented by one for

each AD7280 it passes through on the chain.

To write to the same register on all AD7280’s in the stack bit D3

in the 24-bit write cycle should be set high. This will result in

the 8-bit register data, bits D11-D4, are written to the same

should be regarded as Don’t Care bits when writing to all parts

in the stack. For example when initiating a conversion on all

AD7280s in the stack bit D3 should be set high, the Register

address should be set to Dh, to address the CONTROL register

and bit D11 of the 24-bit write cycle should be set high. This

will initiate a conversion on the rising edge of CS, on all

AD7280s in the stack.

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