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XRT86VL32IB Datasheet(PDF) 95 Page - Exar Corporation |
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XRT86VL32IB Datasheet(HTML) 95 Page - Exar Corporation |
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95 / 154 page  XRT86VL3X 88 REV. 1.2.3 T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION The table below shows configurations of the Transmit Fractional DS1 bit of the Transmit Interface Control Register (TICR). TRANSMIT INTERFACE CONTROL REGISTER (TICR)(ADDRESS = 0XN120H) BIT NUMBER BIT NAME BIT TYPE BIT DESCRIPTION 4 Transmit Fractional DS1 R/W This READ/WRITE bit-field permits the user to determine which one of the two functions the multiplexed I/O pin of TxTSb[0]_n/TxSig_n is spotting. 0 - This pin is configured as TxTSb[0]_n pin, it outputs bit 0 of the timeslot number of the DS1 PCM data that is transmitting. 1 - This pin is configured as TxSig_n pin, it acts as an input source for the signaling bits to be transmitted in the outbound DS1 frames |
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