XRT86VL32IB datasheet(83/154 Pages) EXAR

83 / 154 page

XRT86VL3X

REV. 1.2.3

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

8.2.3

Multiplexed High-Speed Mode

When the Back-plane interface data rate is 12.352Mbit/s, 16.384Mbit/s, HMVIP 16.384Mbit/s, and H.100

16.384Mbit/s, the interface signals are all configured as inputs, except the receive serial data on RxSER and

the multi frame sync pulse provided by the framer. The Back-plane Interface is processing data through

TxSER0 or TxSER4 pins at 12.352Mbit/s or 16.384Mbit/s. The local Terminal Equipment multiplexes payload

and signaling data of every four channels into one serial data stream. Payload and signaling data of Channel 0-

3 are multiplexed onto the Transmit Serial Data pin of Channel 0. Payload and signaling data of Channel 4-7

are multiplexed onto the Transmit Serial Data pin of Channel 4.

Free-running clocks of 12.352MHz are

supplied to the Transmit Input Clock pin of Channel 0 and Channel 4 of the framer. The local Terminal

Equipment provides multiplexed payload data at rising edge of this Transmit Input Clock. The Transmit High-

speed Back-plane Interface of the framer then latches incoming serial data at falling edge of the clock.

Transmit 12.352 Bit-Multiplexed Mode

The local Terminal Equipment maps four 1.544Mbit/s DS1 data streams into one 12.352Mbit/s serial data

stream as described below:

1. The F-bit of four channels are repeated and grouped together to form the first octet of the multiplexed data

stream. The F-bit of Channel 0 is sent first, followed by F-bit of Channel 1 and 2. The F-bit of Channel 3 is

sent last. The table below shows bit-pattern of the first octet.

FX: F-bit of Channel X

2. Payload data of four channels are repeated and grouped together in a bit-interleaved way. The first pay-

load bit of Timeslot 0 of Channel 0 is sent first, followed by the first payload bit of Timeslot 0 of Channel 1

and 2. The first payload bit of Timeslot 0 of Channel 3 is sent last. After the first bits of Timeslot 0 of all four

FIGURE 84. WAVEFORMS FOR CONNECTING THE RECEIVE NON-MULTIPLEXED HIGH-SPEED INPUT INTERFACE AT

MVIP 2.048MBIT/S, 4.096MBIT/S, AND 8.192MBIT/S

BIT PATTERN OF THE FIRST OCTET

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

RxSER

RxSYNC(input)

RxCHCLK(INV)

RxCHN[0]/RxSig

RxCHN[1]/RxFrTD

A B

Don't Care

A B

Don't Care

A B

Don't Care

A B

Don't Care

Note: The following signals are not aligned with the signals shown above. The RxTSClk is derived from 1.544MHz transmit clock.

Don't Care

Don't care

RxSERCLK

(2/4/8MHz)

XRT86VL32IB Datasheet(PDF) 83 Page - Exar Corporation

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