XRT86VL32IB datasheet(73/154 Pages) EXAR

73 / 154 page

XRT86VL3X

REV. 1.2.3

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

can position the beginning of the multiplexed E1 frame. It is responsibility of the Terminal Equipment to align

the multiplexed transmit serial data with the Transmit Single-frame Synchronization pulse.

Inside the framer, all the "don't care" bits will be stripped away. The framing bits, signaling and payload data are

de-multiplexed inside the XRT86VL3x device and send to each individual channel. These data will be

processed by each individual framer and send to LIU interface. The local Terminal Equipment provides a free-

running 2.048MHz clock to the Transmit Serial Input clock of each channel. The framer will use this clock to

carry the processed payload and signaling data to the transmit section of the device.

See Figure 69 below for how to interface the local Terminal Equipment with the Transmit Payload Data Input

Interface block of the framer in HMVIP or H100 16.384Mbit/s mode. Figure 71 shows the timing signals when

the framer is running at HMVIP or H100 16.384 MHz mode.

FIGURE 69. INTERFACING XRT86VL3X TRANSMIT TO LOCAL TERMINAL EQUIPMENT USING 16.384MBIT/S, HMVIP

16.384MBIT/S, AND H.100 16.384MBIT/S

FIGURE 70. TIMING SIGNAL WHEN THE FRAMER IS RUNNING AT BIT-MULTIPLEXED 16.384MBIT/S MODE

TxSER0

TxINCLK0 (16.384MHz)

TxSYNC0

TxSERCLK0 (2.048MHz)

Transmit

Payload

Data Input

Interface

Chn 0

Transmit

Payload

Data Input

Interface

Chn 4

Terminal

Equipment

XRT86VL38

Chn 1

Chn 2

Chn 3

Chn 5

Chn 6

Chn 7

TxSERCLK1 (2.048MHz)

TxSERCLK2 (2.048MHz)

TxSERCLK3 (2.048MHz)

TxSER4

TxINCLK4 (16.384MHz)

TxSYNC4

TxSERCLK4 (2.048MHz)

TxSERCLK5 (2.048MHz)

TxSERCLK6 (2.048MHz)

TxSERCLK7 (2.048MHz)

TxInClk (16.384MHz)

TxInClk (INV)

TxSer

TxSync(input)

0 X 11 X

0 X 21 X

0 X

0 A0 51 A1 52 A2 53 A3

56 cycles

0 X h1 X

8-bit header

XRT86VL32IB Datasheet(PDF) 73 Page - Exar Corporation

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