XRT86VL32IB datasheet(41/154 Pages) EXAR

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XRT86VL3X

REV. 1.2.3

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

The Transmit Data Link Source Select bits of the Transmit Data Link Select Register (TDLSR) controls the

insertion of data link bits into the FDL bits in ESF framing format mode. The table below shows configuration of

the Transmit Data Link Source Select bits of the Transmit Data Link Select Register (TDLSR).

If the Transmit Data Link Source Select bits of the Transmit Data Link Select Register are set to 10, the

Transmit Overhead Input Interface Block becomes input source of the FDL bits.

The XRT86VL3x allows the user to select bandwidth of the Facility Data Link Channel in ESF framing format

mode. The FDL can be either a 4KHz or 2KHz data link channel. The Transmit Data Link Bandwidth Select bits

of the Transmit Data Link Select Register (TDLSR) determine the bandwidth of FDL channel in ESF framing

format mode.

The table below shows configuration of the Transmit Data Link Bandwidth Select bits of the Transmit Data Link

Select Register (TDLSR).)

Figure 35 below shows the timing diagram of the input and output signals associated with the DS1 Transmit

Overhead Input Interface module in ESF framing format mode.

TRANSMIT DATA LINK SELECT REGISTER (TDLSR) (ADDRESS = 0XN10AH)

BIT

NUMBER

BIT NAME

BIT TYPE

BIT DESCRIPTION

1-0

Transmit Data Link

Source Select

R/W

00 - The Facility Data Link bits are inserted into the framer through either

the LAPD controller or the SLC®96 buffer.

01 - The Facility Data Link bits are inserted into the framer through the

Transmit Serial Data input Interface via the TxSer_n pins.

10 - The Facility Data Link bits are inserted into the framer through the

Transmit Overhead Input Interface via the TxOH_n pins.

11 - The Facility Data Link bits are forced to one by the framer.

TRANSMIT DATA LINK SELECT REGISTER (TDLSR) (ADDRESS = 0XN10AH)

BIT

NUMBER

BIT NAME

BIT TYPE

BIT DESCRIPTION

5-4

Transmit Data Link

Bandwidth Select

R/W

00 - The Facility Data Link is a 4KHz channel. All available FDL bits (first

bit of every other frame) are used as data link bits.

01 - The Facility Data Link is a 2KHz channel. Only the odd FDL bits (first

bit of frame 1, 5, 9…) are used as data link bits.

10 - The Facility Data Link is a 2KHz channel. Only the even FDL bits (first

bit of frame 3, 7, 11…) are used as data link bits.

XRT86VL32IB Datasheet(PDF) 41 Page - Exar Corporation

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