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XRT86VL32IB Datasheet(PDF) 31 Page - Exar Corporation |
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XRT86VL32IB Datasheet(HTML) 31 Page - Exar Corporation |
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31 / 154 page ![]() XRT86VL3X 24 REV. 1.2.3 T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION 3.4 Receive HDLC Event Timing The following figure shows the event timing of RxEOT and RxIDLE when receiving HDLC message. 3.5 SS7 (Signaling System Number 7) for ESF in DS1 Only To support SS7 specifications while receiving LAPD messages, EXAR’s Framer will generate an interrupt (if SS7 is enabled) once the HDLC controllers have received more than 276 bytes within two flag sequences (0x7E) of a LAPD message. Each HDLC controller supports SS7. For example: To enable SS7 for all HDLC controllers, registers 0xnB11 (LAPD1), 0xnB19 (LAPD2), 0xnB29 (LAPD3) must be set to 0x01. FIGURE 32. RECEIVE HDLC EVENT TIMING 96-Bytes 4-Bytes 7E 7E 7E 7E 7E LAPD RxEOT RxIDLE 96-Bytes 7E 7E 7E 7E 7E LAPD RxEOT RxIDLE 75-Bytes 7E 7E 7E LAPD RxEOT RxIDLE Figure a. Receiving a 100-Byte Message Figure c. Receiving a 75-Byte Message Figure b. Receiving a 96-Byte Message |
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