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XRT86VL32IB Datasheet(PDF) 44 Page - Exar Corporation |
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XRT86VL32IB Datasheet(HTML) 44 Page - Exar Corporation |
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44 / 154 page ![]() XRT86VL3X 37 T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION REV. 1.2.3 4.2 DS1 Receive Overhead Output Interface Block 4.2.1 Description of the DS1 Receive Overhead Output Interface Block The DS1 Receive Overhead Output Interface Block allows an external device to be the consumer of the Facility Data Link (FDL) bits in ESF framing format mode, Signaling Framing (Fs) bits in the SLC96 and N framing format mode and Remote Signaling (R) bit in T1DM framing format mode This interface provides interface signals and required interface timing to shift out proper data link information at proper time. The Receive Overhead Output Interface for a given Framer consists of two signals. • RxOHClk_n: The Receive Overhead Output Interface Clock Output signal • RxOH_n: The Receive Overhead Output Interface Output signal. The Receive Overhead Output Interface Clock Output pin (RxOHCLK_n) generates a rising clock edge for each data link bit position according to configuration of the framer. The data link bits extracted from the incoming T1 frames are outputted from the Receive Overhead Output Interface Output pin (RxOH_n) at the rising edge of RxOHClk_n. The Data Link equipment should sample and latch the data link bits at the falling edge of RxOHClk_n. The figure below shows block diagram of the Receive Overhead Output Interface of XRT86VL3x. 4.2.2 Configure the DS1 Receive Overhead Output Interface module as destination of the Facility Data Link (FDL) bits in ESF framing format mode The FDL bits in ESF framing format mode can be extracted to: • DS1 Receive Overhead Output Interface Block • DS1 Receive HDLC Controller • DS1 Receive Serial Output Interface. The Receive Data Link Source Select bits of the Receive Data Link Select Register (RDLSR) controls the extraction of FDL bits in ESF framing format mode. The table below shows configuration of the Receive Data Link Source Select bits of the Receive Data Link Select Register (RDLSR). FIGURE 38. BLOCK DIAGRAM OF THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE OF XRT86VL3X Receive Overhead Output Interface RxOH_n RxOHClk_n From Receive Framer Block |
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