XRT86VL32IB datasheet(76/154 Pages) EXAR

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XRT86VL3X

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

REV. 1.2.3

7.3

Brief Discussion of Common Channel Signaling in E1 Framing Format

As the name referred, Common Channel Signaling is signaling information common to all thirty voice or data

channels of an E1 trunk. Time slot 16 may be used to carry Common Channel Signaling data of up to a rate of

64kbits/s. The national bits of time slot 0 may also be used for Common Channel Signaling. Since there are

five national bits of time slot 0 per every two E1 frames, the total bandwidth of the national bits is 20kbits/s. The

Common Channel Signaling is essentially data link information that provides performance monitoring and a

transmission quality report.

7.4

Brief Discussion of Channel Associated Signaling in E1 Framing Format

Signaling is required when dealing with voice and dial-up data services in E1 applications. Traditionally,

signaling is provided on a dial-up telephone line across the talk-path. Signaling is used to tell the receiver

where the call or route is destined. The signal is sent through switches along the route to a distant end.

Common types of signals are:

• On hook

• Off hook

• Dial tone

• Dialed digits

• Ringing cycle

• Busy tone

A signal is consists of four bits namely A, B, C and D. These bits define the state of the call for a particular time

slot. Time slot 16 of each E1 frame can carry CAS signals for two E1 voice or data channels. Therefore,

sixteen E1 frames are needed to carry CAS signals for all 32 E1 channels. The sixteen E1 frames then forms

a CAS Multi-frame.

7.5

Insert/Extract Signaling Bits from TSCR Register

The four most significant bits of the Transmit Signaling Control Register (TSCR) of each time slot can be used

to store outgoing signaling data. The user can program these bits through microprocessor access. If the

XRT86VL3x framer is configure to insert signaling bits from TSCR registers, the E1 Transmit Framer block will

fill up the time slot 16 octet with the signaling bits stored inside the TSCR registers. The insertion of signaling

bit into PCM data is done on a per-channel basis. The most significant bit (Bit 7) of TSCR register is used to

store Signaling bit A. Bit 6 is used to hold Signaling bit B. Bit 5 is used to hold Signaling bit C. Bit 4 is used to

hold Signaling bit D.

7.6

Insert/Extract Signaling Bits from TxCHN[0]_n/TxSIG Pin

The XRT86VL3x framer can be configured to insert/extract signaling bits provided by external equipment

through the external signaling bus. When the Fractional E1 mode is enabled, this bus is configured as TxSIG

and RxSIG. These pins act as an the signaling bus for the outbound E1 frames.

Figure 75 shows a timing diagram of the TxSIG input pin. Figure 76 shows a timing diagram of the RxSIG

output pin. Please note that the Signaling Bit A of a certain channel coincides with Bit 5 of the PCM data of that

channel; Signaling Bit B coincides with Bit 6 of the PCM data; Signaling Bit C coincides with Bit 7 of the PCM

data and Signaling Bit D coincides with Bit 8 (LSB) of the PCM data.

XRT86VL32IB Datasheet(PDF) 76 Page - Exar Corporation

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