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AT697E Datasheet(PDF) 79 Page - ATMEL Corporation |
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AT697E Datasheet(HTML) 79 Page - ATMEL Corporation |
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79 / 154 page  78 AT697E 4226G–AERO–05/09 PLL Overview The CPU clock can be issued from the internal PLL. This PLL contains a phase/fre- quency detector, charge pump, voltage control oscillator, lock detector and divider. Figure 48. PLL Block Diagram The PLL implemented is configured by hardware to provide a cpu clock frequency four times the frequency of the input clock. PLL control The PLL control is done by hardware through dedicated ports, including a bypass, a clock input and a filter input. The following table presents the assignement and functions of the PLL control signals. Table 25. PLL ports description PLL filter To ensure the functionality of the PLL, an external low pass filter shall be connected to the filter input (LFT) of the PLL. Here is a presentation of the filter to setup on the LFT pin. LFT LOCK Divider cpu clock PDIV4 CLK Pin name Function LFT External passive loop filter input LOCK Lock CLK Board clock input BYPASS Bypass |
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