AT697E datasheet(28/154 Pages) ATMEL

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AT697

4226G–AERO–05/09

Write

The write policy for stores is write-through with no-allocate on write-miss. The write buf-

fer (WRB) consists of three 32-bit registers used to temporarily hold store data until it is

sent to the destination device. For half-word or byte stores, the stored data replicated

into proper byte alignment for writing to a word-addressed device, before being loaded

into one of the WRB registers.

The WRB is emptied prior to a load-miss cache-fill sequence to avoid any stale data

from being read in to the data cache.

Read

On a data cache read-miss to a cachable location, 4 bytes of data are loaded into the

cache from main memory.

Cache Flush

Data cache can be flushed by executing the FLUSH instruction, setting logical one the

flush data cache bit (FD) in the cache control register, or writing any location with

ASI=0x6. The flush operation takes one cycle per line during which the IU will is not

halted, but during which the cache is disabled. When the flush operation is completed,

the cache will resume the state indicated in the cache control register.

Error Reporting

Since the processor executes in parallel with the write buffer, a write error will not cause

an exception to the store instruction. Depending on memory and cache activity, the write

cycle may not occur until several clock cycles after the store instructions has completed.

If a write error occurs, the currently executing instruction will take trap 0x2B.

Note:

the 0x2B trap handler should flush the data cache, since a write hit would update the

cache while the memory would keep the old value due the write error.

If a memory access error occurs during a data load, the corresponding valid bit in the

cache tag will not be set. and a data access error trap (tt=0x09) is generated.

Data Cache Parity

Error detection of cache tags and data is implemented using two parity bits per tag and

per 4-byte data sub-block. The tag parity is generated from the tag value and the valid

bits. The data parity is derived from the sub-block data. The parity bits are written simul-

taneously with the associated tag or sub-block and checked on each access. The two

parity bits correspond to the parity of odd and even data (tag) bits.

If a tag parity error is detected during a cache access, a cache miss is generated. The

tag and the data are automatically updated. All valid bits except the one corresponding

to the newly loaded data are cleared. Each error is reported in the instruction cache tag

error counter from the CCR. The data cache tag error counter (DTE) is incremented

after each data cache tag error detection.

If a data sub-block parity error occurs, a miss is also generated but only the failed sub-

block is updated with data from main memory. Each error is reported in the data cache

data error counter from the CCR. The data cache data error counter (DDE) is incre-

mented after each data cache data error detection.

Data Cache Snooper

In addition to the cache controller, a snooper is implemented on the on-chip cache sub-

system. The cache snooper is enabled setting logical one the snoop enable bit (DS) in

the cache control register.

This snooper is able to verify if a master on the internal bus accesses and modifies

some cached data. If a master accesses a data in memory and this data is cached, the

snooper will invalidate the corresponding cache tag. Next time the IU will access the

modified data, a cache miss will be generated due to not valid tag.

AT697E Datasheet(PDF) 28 Page - ATMEL Corporation

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