AT697E datasheet(30/154 Pages) ATMEL

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AT697

4226G–AERO–05/09

Memory Interface

Overview

The AT697 provides a 32-bit bus capable to interface PROM, memories mapped I/O

devices, asynchronous static rams (SRAM) and synchronous dynamic rams (SDRAM).

The memory bus can be configured either for 8-bit, 16-bit, 32-bit or 40-bit accesses. The

memory controller manages up to 2 Gbytes of external memory. The following table

presents the memory controller address map.

Table 13. Memory Controller address map

For applications that require smaller memory areas and/or smaller performances, it is

possible to configure some memory spaces as 8-bit or 16-bit wide data bus.

All the configuration of the memory interface is done through the three memory control-

ler registers : MCFG1, MCFG2 and MCFG3. MCFG1 is the register dedicated to PROM

and IO configuration. SRAM and SDRAM are configured through MCFG2 and MCFG3.

Here is an overview of the 32-bit interconnection between the AT697 and external

memories.

Figure 8. Memory Interface Overview

To improve the bandwidth of the memory bus, accesses to consecutive addresses can

be performed in burst mode. Burst transfers will be generated when the memory control-

ler is accessed using a burst request from the internal bus. These includes instruction

cache-line fills, double loads and double stores. The timing of a burst cycle is identical to

the programmed basic cycle with the exception that during read cycles, the lead-out

cycle will only occurs after the last transfer.

Address Range

Size

Mapping

0x00000000 - 0x1FFFFFFF

512M

PROM

0x20000000 - 0x2FFFFFFF

256M

I/O

0x40000000 - 0x7FFFFFFF

SRAM/SDRAM

PROM

I/O

SRAM

RAMS*[4:0]

RAMOE*[4:0]

RWE*[3:0]

ROMS*[1:0]

OE*

WRITE*

IOS*

AT697

A[27:0]

D[31:0]

RAS

CAS

SDRAM

SDRAS*

SDCAS*

SDWE*

A[16:15]

DQM

SDDQM[3:0]

CLK

CSN

SDCLK

SDCSN[1:0]

A[14:2]

AT697E Datasheet(PDF) 30 Page - ATMEL Corporation

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