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AT697E Datasheet(PDF) 42 Page - ATMEL Corporation

Part # AT697E
Description  Rad-Hard 32 bit SPARC V8 Processor
PDF  154 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT697E Datasheet(HTML) 42 Page - ATMEL Corporation

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41
AT697
4226G–AERO–05/09
Write Protection
Read and write protections are provided to prevent accidental accesses to I/O area.
Protection is controlled through the I/O protection ‘iop’ bit from the memory configuration
register 1.
Bus width
To support applications with low memory and performance requirements, I/O area can
be configured for 8-bit operations. The configuration of I/O in 8-bit mode is done pro-
gramming the I/O bus width field in he memory configuration registers MCFG1.
In such configuration, I/O device is not accessed by multiple 8-bit accesses as other
memory areas. Only one single access is performed
When the I/O bus is configured as an 8-bit wide bus, data 31 downto 24 shall be used as
interface.
Figure 26. I/O 8-bit bus width connection
In addition to the 8-bit mode, the I/O area can be configured for 16-bit accesses. In such
configuration, I/O device is not accessed by multiple 8-bit accesses as other memory
areas. Only one single access is performed.
When the bus is configured as an 16-bit wide bus, data 31 downto 16 shall be used as
interface.
Figure 27. I/O 16-bit bus width connection
Access Error
An access error can be indicated to the processor asserting the BEXC* signal. If
enabled by setting logical one the BEXC* bit in the memory configuration register 1, the
BEXC* signal is sampled with the data.
•
Trap 0x01 is taken if an instruction fetch is in progress
•
Trap 0x09 is taken if a data space is in progress
•
Trap 0x2B is taken if a data store is in progress
Error Management -
EDAC
Overview
The AT697 processor implements an on-chip error detector and corrector (EDAC). The
on-chip memory EDAC can correct one error in a 32-bit word and detect two errors in a
32-bit word. The processor EDAC implemention enables data correction on-the-fly so
that no timing penalty occurs during correction.
CS
OE
WE
A
D
IO
OE*
AD
AT697
A[27:0]
D[31:24]
D[31:24]
A[27:0]
WRITE*
IOS*
CS
OE
WE
A
D
IO
OE*
AD
AT697
A[27:0]
D[31:16]
D[31:16]
A[27:0]
WRITE*
IOS*



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