AT697E datasheet(34/154 Pages) ATMEL

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AT697

4226G–AERO–05/09

Figure 14. SRAM 8-bit bus width connection

Since access to memory is always done on 32-bit word basis, read access to 8-bit mem-

ory will be transformed in a burst of four read cycles. If EDAC protection is active, 5 read

cycles are necessary to complete the access (please refer to “Error Management -

EDAC” on page 41 for more details). During write operation, only the necessary bytes

are writen.

In addition to the 8-bit mode, the SRAM area can be configured for 16-bit accesses. In

this configuration, the SRAM device is accessed with a burst of two 16-bit accesses. No

EDAC protection can be used with suh configuration.

When the bus is configured as an 16-bit wide bus, data 31 downto 16 shall be used as

interface.

Figure 15. SRAM 16-bit bus width connection

Write Protection

Write protection is provided to prevent accidental over-writing to the RAM area. Two

block protection units are available for RAM area. Each one is controlled through a write

protection register (WPRn). Two major fields are defined : a TAG and a MASK.

•

The TAG defines the 15 most significant bits of the address of the block to be write

protected.

•

The Mask specifies which bits of the TAG are really relevant for the protection.

Operation

The write protection on the RAM area is enabled setting logical one the enable bit (EN)

in the write protect register (WPRn). If this bit is set logical zero, no protection is

activated.

Two protection modes can be programmed. If the block protect bit (BP) of the write pro-

tect register (WPRn) is set logical one the protection is active within the segment. If the

BP bit is set logical zero, the exterior of the segment is protected.

SRAM

RAMOE0*

AT697

A[27:0]

D[31:24]

A[27:0]

RWE0*

RAMS0*

SRAM

RAMOE0*

AT697

A[27:0]

D[31:24]

D[31:16]

A[27:1]

RWE0*

RAMS0*

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