AT697E datasheet(53/154 Pages) ATMEL

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AT697E

4226G–AERO–05/09

PCI Interface

Overview

The PCI interface implementation is compliant with the PCI 2.2 specification. It is a high

performance 32-bit bus interface with multiplexed address and data lines. It is intended

for use as an interconnect mechanism between processor/memory systems and periph-

eral controller components.

The AT697 processor embedds the In-Silicon PCI core. It is interfaced to the processor

core through the PCI to AMBA bridge developped by the European Space Agency.

The PCI bus operations can be clocked at a frequency up to 33MHz, independently of

the processor clock. Synchronization of the operation between PCI interface and AT697

core implies numerous FIFO usage. This implementation allows to use the device for

Initiator (Master) and Target operations. In each mode single word and burst transfer

can be executed.

Two different operating modes can be used with the PCI interface :

•

Host Bridge

The host-bridge connects the local bus of a processor to the PCI bus. Its PCI

configuration registers are accessible locally by the processor, but not through PCI

configuration cycles. Host-bridge initialises other satellite devices through PCI

configuration commands.

•

Sattelite

The satellite is a PCI device, configurable via PCI configuration cycles and the idsel

line, but not locally.

Both, host-bridge and satellites can be initiator and/or target on the bus. The present

interface has universal functionality, allowing both operation modes. The mode is config-

ured via an hardware bootstrap on the SYSEN* pin.

Some other features are supported by this interface like

•

Target lock support

•

Zero-latency Fast Back-to-Back transfers

•

Zero wait state burst mode transfers

•

Support for memory read line/multiple

•

Support for memory write and invalidate commands

•

Delayed read support

•

Flexible error reporting by polling

The PCI bus is a multiplexed one. In this way, address and data through the same

medium. That is why PCI communication is based on two phase burst transfer. Each

transfer is composed of the following phases :

•

An address phase

During the address phase, the initiator of the communication drives the 32-bit

address concerned by the transfer and the command involved through this transfer.

The command defines the space area concerned with the transfer and the direction

of the transfer.

•

A data phase

During the data phase the initiator of the communication drives the enable bit signal

so that only active part of the bus is enabled. When reading, the initiator drives the

enable bits and the target set the data on the bus.

AT697E Datasheet(PDF) 53 Page - ATMEL Corporation

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