AT697E datasheet(23/154 Pages) ATMEL

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AT697

4226G–AERO–05/09

Asynchronous Traps /

Interrupts

The AT697 handles 11 interrupts. Interrupts can be due to external interrupt requests

not directly related to any particular instruction or can be due to exception caused by

particular previously executed instruction.

Figure 7. Interrupt Controller Block Diagram

Operation

When an interrupt is generated, the corresponding bit is set in the interrupt pending reg-

ister (ITP). The pending bits are ANDed with the interrupt mask register and then

forwarded to the priority selector. The highest interrupt from priority level 1 will be for-

warded to the IU - if no unmasked pending interrupt exists on priority level 1, then the

highest unmasked interrupt from priority level 0 is forwarded.

When the IU acknowledges the interrupt, the corresponding pending bit will automati-

cally be cleared.

Interrupt can also be forced by setting a bit in the interrupt force register. In this case,

the IU acknowledgement will clear the force bit rather than the pending bit.

After reset, the interrupt mask register is set to all zeros while the remaining control reg-

isters are undefined.

Interrupt List

The following table presents the assignement of the interrupts.

Table 9. Interrupt Overview

Interrupt Pending Reg.

ITP

Interrupt Force Reg.

ITF

Interrupt Mask & Priority Reg.

ITMP

Interrupt Clear Reg.

ITC

I/O Interrupt Reg.

IOIT

priority

mask

trap1x generation

PIO[15:0]

Internal Interrupt

(Timer1, Uart1,...)

Interrupt Sources

Interrupt

TT (Trap Type)

Source

0x1F

unused

0x1E

PCI

0x1D

unused

0x1C

unused

0x1B

DSU trace buffer

0x1A

unused

0x19

Timer 2

0x18

Timer 1

0x17

I/O interrupt [3]

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