AT697E datasheet(62/154 Pages) ATMEL

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AT697

4226G–AERO–05/09

Figure 37. Data frame format

Parity bit

The parity bit is calculated by doing an exclusive-or of all the data bits. The odd parity is config-

ured setting logical one the PS bit in the uart control register (UACn). In this case, the result of

the exclusive or is inverted. An even parity can be selected setting logical zero the PS bit.

If used, the parity bit is located between the last data bit and the stop bit of the serial frame.

The relation between the parity bit and data bits is as follows:

Peven

Parity bit using even parity

Podd

Parity bit using odd parity

Data bit n of the character

Clock Generation

The clock generation logic generates the base clock for the Transmitters and Receivers. The bit

rate of the UART is issued from the clock generator after a combination between the input clock

of the clock module and a scaler.

Uart Clock

Two clock inputs can be used by the clock generator :

•

An internal clock

•

An external clock

Each UART can be configured to use either the internal or the external clock source by

programming the EC bit in the uart control register (UACn). If set logical zero, the UART

is clocked by the internal clock. If EC is set logical one, the UART is clocked by the

external clock. When using the external configuration, the UART clock shall be provided

by PIO[3] from the general purpose interface. This clock input is used as an alternate

function for PIO[3].

caution :

When using the external clock source, the frequency of PIO[3] must be less than half the

frequency of the system clock.

Baud Rate Generation

To generate the bit-rate, each UART has a programmable 12-bits clock divider (UAS-

CAn). According to the configuration of the EC bit in the uart control register, the scaler

is clocked either by the system or by an external clock.

Each time the scaler underflows, a UART tick is generated. The scaler is automatically

reloaded with the value of the UART scaler register after each underflow. The resulting

UART tick frequency should be 8 times the desired baud-rate.

Start D0

Stop

Start D0

Stop

Parity

Data frame, no parity:

Data frame with parity:

Peven

d7 … d3 d2 d1 d0 0

Podd

⊕

⊕⊕⊕⊕⊕

d7 … d3 d2 d1 d0 1

⊕

⊕⊕⊕⊕⊕

AT697E Datasheet(PDF) 62 Page - ATMEL Corporation

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