AT697E datasheet(46/154 Pages) ATMEL

46 / 154 page

AT697

4226G–AERO–05/09

Timer Unit

Prescaler

Timer/Counter1, Timer/Counter2 and the watchdog share the same prescaler.

The prescaler consists of a 10-bit down counter clocked by the system clock. The pres-

caler is decremented on each clock cycle. When the prescaler underflows, it is

automatically reloaded with the content of the prescaler reload register. A count tick is

generated for the two timers and the watchdog.

The effective division rate is equal to prescaler reload register value + 1.

Figure 30. Prescaler Block Diagram

Caution :

The two timers and watchdog share the same decrementer. The minimum allowed pres-

caler division factor is 4 (reload register = 3).

Timer/Counter 1 &

Timer/Counter 2

Timer/Counter1, Timer/Counter2 are two general purpose 24-bit timers. They share the

same decrementer. The timer value is then decremented each time the prescaler gener-

ates a timer pulse.

Each timer operation is controlled through a dedicated Timer Control register (TIMCTR).

A timer is enabled/disabled by setting the enable bit (en) in the timer control register.

Each time a timer underflows, an interrupt is generated. These interrupts can be

masked with the Interrupt Mask and Priority register (ITMP).

Setting the load bit (rl) in the Timer Control register, the content of the reload register

(TIMR) is automatically reloaded in the Timer Counter register (TIMC) after an under-

flow and the timer continue running. If the reload bit is reset, the timer stops running

after its first underflow.

Timer Counter can be forced with the Timer Reload value at any time by asserting the

load bit (ld) in the Timer Control register.

Control Logic

Reload Reg.

Counter Reg.

=0x3FF

clock

count tick

load

SCAR

SCAC

AT697E Datasheet(PDF) 46 Page - ATMEL Corporation