ATmega32U2 datasheet(102/314 Pages) ATMEL

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102

7799B–AVR–07/09

ATmega8U2/16U2/32U2

15.9

15.9.1

TCCR0A – Timer/Counter Control Register A

• Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0

bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin

must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A[1:0] bits depends on the

WGM0[2:0] bit setting. Table 15-2 shows the COM0A[1:0] bit functionality when the WGM0[2:0]

bits are set to a normal or CTC mode (non-PWM).

Table 15-3 shows the COM0A[1:0] bit functionality when the WGM0[1:0] bits are set to fast

PWM mode.

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 97

for more details.

Bit

210

0x24 (0x44)

COM0A1

COM0A0

COM0B1

COM0B0

–

WGM01

WGM00

TCCR0A

Read/Write

R/W

Initial Value

Table 15-2.

Compare Output Mode, non-PWM Mode

COM0A1

COM0A0

Description

Normal port operation, OC0A disconnected.

Toggle OC0A on Compare Match

Clear OC0A on Compare Match

Set OC0A on Compare Match

Table 15-3.

Compare Output Mode, Fast PWM Mode

(1)

COM0A1

COM0A0

Description

Normal port operation, OC0A disconnected.

WGM02 = 0: Normal Port Operation, OC0A Disconnected.

WGM02 = 1: Toggle OC0A on Compare Match.

Clear OC0A on Compare Match, set OC0A at TOP

Set OC0A on Compare Match, clear OC0A at TOP

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