ATmega32U2 datasheet(105/314 Pages) ATMEL

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105

7799B–AVR–07/09

ATmega8U2/16U2/32U2

15.9.2

TCCR0B – Timer/Counter Control Register B

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is

changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a

strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the

forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0A as TOP.

The FOC0A bit is always read as zero.

• Bit 6 – FOC0B: Force Output Compare B

The FOC0B bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is

changed according to its COM0B[1:0] bits setting. Note that the FOC0B bit is implemented as a

strobe. Therefore it is the value present in the COM0B[1:0] bits that determines the effect of the

forced compare.

A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0B as TOP.

The FOC0B bit is always read as zero.

• Bits 5:4 – Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bit 3 – WGM02: Waveform Generation Mode

See the description in the “TCCR0A – Timer/Counter Control Register A” on page 102.

• Bits 2:0 – CS0[2:0]: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

Bit

210

0x25 (0x45)

FOC0A

FOC0B

–

WGM02

CS02

CS01

CS00

TCCR0B

Read/Write

R/W

Initial Value

Table 15-9.

Clock Select Bit Description

CS02

CS01

CS00

Description

No clock source (Timer/Counter stopped)

001

clkI/O/(No prescaling)

010

clkI/O/8 (From prescaler)

011

clkI/O/64 (From prescaler)

ATmega32U2 Datasheet(PDF) 105 Page - ATMEL Corporation

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