ATmega32U2 datasheet(131/314 Pages) ATMEL

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7799B–AVR–07/09

ATmega8U2/16U2/32U2

Note:

A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and

COMnA1/COMnB1//COMnC1 is set. See “Phase Correct PWM Mode” on page 99. for more

details.

• Bit 1:0 – WGMn1:0: Waveform Generation Mode

Combined with the WGMn[3:2] bits found in the TCCRnB Register, these bits control the count-

ing sequence of the counter, the source for maximum (TOP) counter value, and what type of

waveform generation to be used, see Table 16-4. Modes of operation supported by the

Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,

and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page

96.).

Table 16-3.

Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM

COMnA1/COMnB/

COMnC1

COMnA0/COMnB0/

COMnC0

Description

Normal port operation, OCnA/OCnB/OCnC

disconnected.

WGM1[3:0] = 8, 9 10 or 11: Toggle OC1A on

Compare Match, OC1B and OC1C disconnected

(normal port operation). For all other WGM1

settings, normal port operation,

OC1A/OC1B/OC1C disconnected.

Clear OCnA/OCnB/OCnC on compare match

when up-counting. Set OCnA/OCnB/OCnC on

compare match when downcounting.

Set OCnA/OCnB/OCnC on compare match when

up-counting. Clear OCnA/OCnB/OCnC on

compare match when downcounting.

ATmega32U2 Datasheet(PDF) 131 Page - ATMEL Corporation