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ATmega32U2 Datasheet(PDF) 132 Page - ATMEL Corporation |
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ATmega32U2 Datasheet(HTML) 132 Page - ATMEL Corporation |
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132 / 314 page ![]() 132 7799B–AVR–07/09 ATmega8U2/16U2/32U2 Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. Table 16-4. Waveform Generation Mode Bit Description(1) Mode WGMn3 WGMn2 (CTCn) WGMn1 (PWMn1) WGMn0 (PWMn0) Timer/Counter Mode of Operation TOP Update of OCRn x at TOVn Flag Set on 0 0 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCRnA Immediate MAX 5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP 6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP 7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP 8 100 0 PWM, Phase and Frequency Correct ICRn BOTTOM BOTTOM 9 100 1 PWM, Phase and Frequency Correct OCRnA BOTTOM BOTTOM 10 1 0 1 0 PWM, Phase Correct ICRn TOP BOTTOM 11 1 0 1 1 PWM, Phase Correct OCRnA TOP BOTTOM 12 1 1 0 0 CTC ICRn Immediate MAX 13 110 1 (Reserved) – – – 14 1 1 1 0 Fast PWM ICRn TOP TOP 15 1 1 1 1 Fast PWM OCRnA TOP TOP |
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