ATmega32U2 datasheet(137/314 Pages) ATMEL

137 / 314 page

137

7799B–AVR–07/09

ATmega8U2/16U2/32U2

• Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output

Compare Register B (OCRnB).

Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB Flag.

OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is exe-

cuted. Alternatively, OCFnB can be cleared by writing a logic one to its bit location.

• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn value matches the Output Com-

pare Register A (OCRnA).

Note that a Forced Output Compare (FOCnA) strobe will not set the OCFnA Flag.

OCFnA is automatically cleared when the Output Compare Match A Interrupt Vector is exe-

cuted. Alternatively, OCFnA can be cleared by writing a logic one to its bit location.

• Bit 0 – TOVn: Timer/Countern, Overflow Flag

The setting of this flag is dependent of the WGMn[3:0] bits setting. In Normal and CTC modes,

the TOVn Flag is set when the timer overflows. Refer to Table 16-4 on page 132 for the TOVn

Flag behavior when using another WGMn[3:0] bit setting.

TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed.

Alternatively, TOVn can be cleared by writing a logic one to its bit location.

ATmega32U2 Datasheet(PDF) 137 Page - ATMEL Corporation