ATmega32U2 datasheet(220/314 Pages) ATMEL

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7799B–AVR–07/09

ATmega8U2/16U2/32U2

This flag is set by the USB controller when the current bank contains a new packet. This

RXOUTI flag can generate a “USB endpoint interrupt” if RXOUTE bit is set. Writing this bit to

zero acknowledges the interrupt source (USB clocks must be enabled before). Writing this bit to

one has no effect for an OUT endpoint.

• Endpoint IN direction (KILLBK bit)

Writing this bit to one kills the last loaded bank. This sequence can be used to cancelled a previ-

ously loaded endpoint. Clearing by software has no effect. See page 206 for more details on the

Abort.

• Bit 1 – STALLEDI: STALLEDI Interrupt Flag

This flag is set by the USB controller when STALL handshake has been sent, or when a CRC

error has been detected for an isochronous OUT endpoint. This STALLEDI flag can generate a

“USB endpoint interrupt” if STALLEDE bit is set. Writing this bit to zero acknowledges the inter-

rupt source (USB clocks must be enabled before). Writing this bit to one has no effect.

• Bit 0 – TXINI: Transmitter Ready Interrupt Flag

This flag is set by the USB controller when the current bank is free and can be filled. This TXINI

flag can generate a “USB endpoint interrupt” if TXINE bit is set. Writing this bit to zero acknowl-

edges the interrupt source (USB clocks must be enabled before). Writing this bit to one has no

effect.

21.18.16 UEIENX – USB Endpoint Interrupt Enable Register

• Bit 7 – FLERRE: Flow Error Interrupt Enable Flag

Writing this bit to one enables interrupt on OVERFI or UNDERFI flags. An overflow or underflow

interrupt will be generated only if the FLERRE bit is set to one, the Global Interrupt Flag in SREG

is written to one, and the OVERFI or UNDERFI flags are set.

• Bit 6 – NAKINE: NAK IN Interrupt Enable Bit

Writing this bit to one enables interrupt on NAKINI flag. A NAK IN interrupt will be generated only

if the NAKINE bit is set to one, the Global Interrupt Flag in SREG is written to one, and the

NAKINI is set.

• Bit 5 – Res: Reserved

This bit is reserved and will always read as zero.

• Bit 4 – NAKOUTE: NAK OUT Interrupt Enable Bit

Writing this bit to one enables interrupt on NAKOUTI flag. A NAKOUT interrupt will be generated

only if the NAKOUTE bit is set to one, the Global Interrupt Flag in SREG is written to one, and

the NAKOUTI is set.

Bit

321

(0xF0)

FLERRE

NAKINE

NAKOUTE

RXSTPE

RXOUTE

STALLEDE

TXINE

UEIENX

Read/Write

R/W

Initial Value

ATmega32U2 Datasheet(PDF) 220 Page - ATMEL Corporation

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