ATmega32U2 datasheet(217/314 Pages) ATMEL

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7799B–AVR–07/09

ATmega8U2/16U2/32U2

21.18.13 UESTA0X – USB Endpoint Status 0 Register

• Bit 7 – CFGOK: Configuration Status Flag

This flag bit is set by hardware when the selected endpoint size parameter (EPSIZE) and num-

ber of banks (EPBK) are correct compared to the max FIFO capacity. This bit is updated when

the bit ALLOC is set, if the USB controller can not allocate the correct amount of memory for the

selected endpoint, this flag bit will be cleared.

If this bit is cleared, the user should reprogram the UECFG1X register with correct EPSIZE and

EPBK values.

• Bit 6 – OVERFI: Overflow Error Interrupt Flag

This flag is set when an overflow error occurs for an isochronous endpoint.This OVERFI flag can

generate a “USB endpoint interrupt” if FLERRE bit is set. Writing this bit to zero acknowledges

the interrupt source (USB clocks must be enabled before). Writing this bit to one has no effect.

See “Isochronous mode” on page 207 for more details.

• Bit 5 – UNDERFI: Underflow Error Interrupt Flag

This flag is set when an underflow error occurs for an isochronous endpoint.This UNDERFI flag

can generate a “USB endpoint interrupt” if FLERRE bit is set. Writing this bit to zero acknowl-

edges the interrupt source (USB clocks must be enabled before). Writing this bit to one has no

effect.

See “Isochronous mode” on page 207 for more details.

• Bit 4 – Res: Reserved

This bit is reserved and will always read as zero.

• Bit 3:2 – DTSEQ[1:0]: Data Toggle Sequencing Flag

These flags are set by hardware to indicate the PID data of the current bank as shown in Table

21-5.

For OUT transfer, this value indicates the last data toggle received on the current bank. For IN

transfer, it indicates the Toggle that will be used for the next packet to be sent. This is not rela-

tive to the current bank.

Bit

321

(0xEE)

CFGOK

OVERFI

UNDERFI

DTSEQ1:0

NBUSYBK1:0

UESTA0X

Read/Write

R/W

Initial Value

Table 21-5.

DTSEQ[1:0] Bits Settings

DTSEQ1

PID DATA

DATA0

DATA1

Reserved.

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