ATmega32U2 datasheet(215/314 Pages) ATMEL

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215

7799B–AVR–07/09

ATmega8U2/16U2/32U2

• Bit 4 – STALLRQC: STALL Request Clear Handshake Bit

Writing this bit to one disables the pending STALL handshake mechanism triggered by

STALLRQ bit. This bit can not be write to zero, it is cleared by hardware immediately after the

write to one operation.

See “STALL request” on page 201 for more details.

• Bit 3 – RSTDT: Reset Data Toggle Bit

Writing this bit to one allows to reset the data toggle bit field for the selected endpoint. This bit

can not be write to zero, it is cleared by hardware immediately after the write to one operation.

• Bits 2:1 – Res: Reserved

These bits are reserved and will always read as zero.

• Bit 0 – EPEN: Endpoint Enable Bit

Writing this bit to one enables the selected endpoint. When the endpoint is enabled it can be

configured and used by the USB controller. Endpoint 0 shall always be enabled after a hardware

or USB reset and participate in the device configuration. Writing this bit to zero disables the cur-

rent endpoint.

See “Endpoint activation” on page 198 for more details.

21.18.11 UECFG0X – USB Endpoint Configuration 0 Register

• Bit 7:6 – EPTYPE[1:0]: Endpoint Type Bits

These bits configure the endpoint type for the selected endpoint as shown in Table 21-2.

• Bits 5:1 – Res: Reserved

These bits are reserved and will always read as zero.

• Bit 0 – EPDIR: Endpoint Direction Bit

Writing this bit to one configures the selected endpoint in the IN direction. Writing this bit to zero

configure the endpoint in the OUT direction. This bit is relevant for bulk, interrupt or isochronous

endpoints. Using this bit with a control endpoint has no effect (control endpoints are

bidirectional).

Bit

321

(0xEC)

EPTYPE1:0

EPDIR

UECFG0X

Read/Write

R/W

Initial Value

Table 21-2.

EPTYPE[1:0] Bits Settings

EPTYPE1

EPTYPE0

Endpoint Type Configuration

Control Type

Bulk Type

Isochronous Type

Interrupt Type

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