ATmega32U2 datasheet(212/314 Pages) ATMEL

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212

7799B–AVR–07/09

ATmega8U2/16U2/32U2

• Bit 5 – EORSME: End Of Resume Interrupt Enable Bit

Writing this bit to one enables interrupt on EORSMI flag. An end of resume Upstream resume

interrupt will be generated only if the EORSME bit is set to one, the Global Interrupt Flag in

SREG is written to one, and the EORSMI bit is set.

• Bit 4 – WAKEUPE: Wake-up CPU Interrupt Enable Bit

Writing this bit to one enables interrupt on WAKEUPI flag. A wake-up interrupt will be generated

only if the WAKEUPE bit is set to one, the Global Interrupt Flag in SREG is written to one, and

the WAKEUPI bit is set.

• Bit 3 – EORSTE: End Of Reset Interrupt Enable Bit

Writing this bit to one enables interrupt on EORSTI flag. A USB reset interrupt will be generated

only if the EORSTE bit is set to one, the Global Interrupt Flag in SREG is written to one, and the

EORSTI bit is set.

• Bit 2 – SOFE: Start Of Frame Interrupt Enable Bit

Writing this bit to one enables interrupt on SOFI flag. A Start of Frame USB reset interrupt will be

generated only if the SOFE bit is set to one, the Global Interrupt Flag in SREG is written to one,

and the SOFI bit is set.

• Bit 1 – Res: Reserved

This bit is reserved and will always read as zero.

• Bit 0 – SUSPE: Suspend Interrupt Enable Bit

Writing this bit to one enables interrupt on SUSPI flag. A suspend interrupt will be generated

only if the SUSPE bit is set to one, the Global Interrupt Flag in SREG is written to one, and the

SUSPI bit is set.

21.18.4

UDADDR – USB Device Address Register

• Bit 7 – ADDEN: Address Enable Bit

Writing this bit to one will enable the UADD[6:0] field as device address for the USB controller.

When this bit is set the USB device controller will be able to answer all requests on the USB that

refer to the UADD[6:0] USB bus address.

See “Address Setup” on page 199 for more details.

• Bits 6:0 – UADD[6:0]: USB Address Bits

These bits contain the USB device address, thatthe USB controller should answer on the USB

bus. This address should be enabled writing one to the ADDEN bit.

Bit

6543

210

(0xE3)

ADDEN

UADD[6:0]

UDADDR

Read/Write

R/W

RRRRRR

Initial Value

0000

000

ATmega32U2 Datasheet(PDF) 212 Page - ATMEL Corporation

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