ATmega32U2 datasheet(210/314 Pages) ATMEL

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210

7799B–AVR–07/09

ATmega8U2/16U2/32U2

• Bits 7:3 – Res: Reserved

These bits are reserved and will always read as zero.

• Bit 2 – RSTCPU: USB Reset CPU Bit

Writing this bit to one allows the CPU controller to reset the CPU when a USB bus reset condi-

tion is detected. When this mode is activated, the next USB bus reset event allows to reset the

CPU and all peripherals except the USB controller. This mode allows to perform a software

reset, but keep the USB device attached to the bus.

This bit is reset when the USB controller is disabled or when writing this bit to zero by firmware.

Writing this bit to zero makes the CPU system reset independent from the USB bus reset event.

• Bit 1 – RMWKUP: Remote Wake-up Bit

Writing this bit to one allows the USB controller to generate an “upstream-resume” packet on the

USB bus. This bit is immediately cleared by hardware and can not be read back to one. Writing

this bit to zero has no effect.

See “Remote Wake-up” on page 201 for more details.

• Bit 0 – DETACH: Detach Bit

Writing this bit to one (default value) disables the USB D+ internal pull-up. This makes the USB

device controller physically “detached” from the USB bus. Writing this bit to zero enables the D+

internal pull-up and physically connects the USB device controller to the USB bus. See “Detach”

on page 200 for more details.

21.18.2

UDINT – USB Device Interrupt Register

• Bit 7 – Res: Reserved

This bit is reserved and should always read as zero.

• Bit 6 – UPRSMI: Upstream Resume Interrupt Flag

This flag is set by hardware when the USB controller has successfully sent the Upstream

Resume sequence (See description of “Bit 1 – RMWKUP: Remote Wake-up Bit” on page 210). If

UPRSME is set, the UPRSMI flag can generate a “USB general interrupt”. Writing this bit to zero

acknowledges the interrupt source (USB clocks must be enabled before). Writing this bit to one

has no effect.

• Bit 5 – EORSMI: End Of Resume Interrupt Flag

This flag is set by hardware when the USB controller detects an End Of Resume sequence on

the USB initiated by the host. If the EORSME bit is set, the EORSMI flag can generate a “USB

general interrupt”. Writing this bit to zero acknowledges the interrupt source (USB clocks must

be enabled before). Writing this bit to one has no effect.

Bit

(0xE1)

UPRSMI

EORSMI

WAKEUPI

EORSTI

SOFI

SUSPI

UDINT

Read/Write

R/W

Initial Value

ATmega32U2 Datasheet(PDF) 210 Page - ATMEL Corporation

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