ATmega32U2 datasheet(207/314 Pages) ATMEL

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207

7799B–AVR–07/09

ATmega8U2/16U2/32U2

• In a control transaction: ZLP data OUT received during a IN stage,

• In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN

stage on the IN endpoint

The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort is to per-

form the following operations:

Table 21-1.

Abort flow

21.15 Isochronous mode

21.15.1

Underflow

An underflow can occur during IN stage if the host attempts to read a bank which is empty. In

this situation, the UNDERFI interrupt is triggered.

An underflow can also occur during OUT stage if the host send a packet while the banks are

already full. Typically, he CPU is not fast enough. The packet is lost.

It is not possible to have underflow error during OUT stage, in the CPU side, since the CPU

should read only if the bank is ready to give data (RXOUTI=1 or RWAL=1)

21.15.2

CRC Error

A CRC error can occur during OUT stage if the USB controller detects a bad received packet. In

this situation, the STALLEDI interrupt is triggered. This does not prevent the RXOUTI interrupt

from being triggered.

21.16 Overflow

In Control, Isochronous, Bulk or Interrupt Endpoint, an overflow can occur during OUT stage, if

the host attempts to write in a bank that is too small for the packet. In this situation, the OVERFI

interrupt is triggered (if enabled). The packet is acknowledged and the RXOUTI interrupt is also

triggered (if enabled). The bank is filled with the first bytes of the packet.

Endpoint

Abort

Abort done

Abort is based on the fact

that no banks are busy,

meaning that nothing has to

be sent.

Disable the TXINI interrupt.

Endpoint

reset

NBUSYBK

Yes

Clear

UEIENX.

TXINE

KILLBK=1

Yes

Kill the last written

bank.

Wait for the end of the

procedure.

ATmega32U2 Datasheet(PDF) 207 Page - ATMEL Corporation

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