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ATmega32U2 Datasheet(PDF) 204 Page - ATMEL Corporation |
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ATmega32U2 Datasheet(HTML) 204 Page - ATMEL Corporation |
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204 / 314 page  204 7799B–AVR–07/09 ATmega8U2/16U2/32U2 21.13.1.1 “Manual” mode Each time the current bank is full, the RXOUTI and the FIFOCON bits are set. This triggers an interrupt if the RXOUTE bit is set. The firmware can acknowledge the USB interrupt by clearing the RXOUTI bit. The Firmware read the data and clear the FIFOCON bit in order to free the cur- rent bank. If the OUT Endpoint is composed of multiple banks, clearing the FIFOCON bit will switch to the next bank. The RXOUTI and FIFOCON bits are then updated by hardware in accordance with the status of the new bank. RXOUTI shall always be cleared before clearing FIFOCON. The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can read data from the bank, and cleared by hardware when the bank is empty. 21.13.2 Detailed description The data are read by the CPU, following the next flow: • When the bank is filled by the host, an endpoint interrupt (EPINTx) is triggered, if enabled (RXOUTE set) and RXOUTI is set. The CPU can also poll RXOUTI or FIFOCON, depending on the software architecture, • The CPU acknowledges the interrupt by clearing RXOUTI, • The CPU can read the number of byte (N) in the current bank (N=BYCT), • The CPU can read the data from the current bank (“N” read of UEDATX), OUT DATA (to bank 0) ACK RXOUTI FIFOCON HW OUT DATA (to bank 0) ACK HW SW SW SW Example with 1 OUT data bank read data from CPU BANK 0 OUT DATA (to bank 0) ACK RXOUTI FIFOCON HW OUT DATA (to bank 1) ACK SW SW Example with 2 OUT data banks read data from CPU BANK 0 HW SW read data from CPU BANK 0 read data from CPU BANK 1 NAK |
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