ATmega32U2 datasheet(202/314 Pages) ATMEL

202 / 314 page

202

7799B–AVR–07/09

ATmega8U2/16U2/32U2

21.11.2

STALL handshake and Retry mechanism

The Retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the

STALLRQ request bit is set and if there is no retry required.

21.12 CONTROL endpoint management

A SETUP request is always ACK’ed. When a new setup packet is received, the RXSTPI inter-

rupt is triggered (if enabled). The RXOUTI interrupt is not triggered.

The FIFOCON and RWAL fields are irrelevant with CONTROL endpoints. The firmware shall

thus never use them on that endpoints. When read, their value is always 0.

CONTROL endpoints are managed by the following bits:

• RXSTPI is set when a new SETUP is received. It shall be cleared by firmware to

acknowledge the packet and to clear the endpoint bank.

• RXOUTI is set when a new OUT data is received. It shall be cleared by firmware to

acknowledge the packet and to clear the endpoint bank.

• TXINI is set when the bank is ready to accept a new IN packet. It shall be cleared by firmware

to send the packet and to clear the endpoint bank.

CONTROL endpoints should not be managed by interrupts, but only by polling the status bits.

21.12.1

Control Write

The next figure shows a control write transaction. During the status stage, the controller will not

necessary send a NAK at the first IN token:

• If the firmware knows the exact number of descriptor bytes that must be read, it can then

anticipate on the status stage and send a ZLP for the next IN token,

• or it can read the bytes and poll NAKINI, which tells that all the bytes have been sent by the

host, and the transaction is now in the status stage.

SETUP

RXSTPI

RXOUTI

TXINI

USB line

OUT

NAK

DATA

SETUP

STATUS

ATmega32U2 Datasheet(PDF) 202 Page - ATMEL Corporation