ST7541 datasheet(17/78 Pages) SITRONIX

17 / 78 page

ST7541

Ver 1.9

17/78

2007/9/3

[ START AND STOP CONDITIONS ]

When the bus is not busy, both SDA and SCL lines remain HIGH. A HIGH-to-LOW transition of SDA, while SCL is HIGH is

defined as the START condition (S). A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition

(P). The START and STOP conditions are illustrated in Figure 4.

[ SYSTEM CONFIGURATION ]

The system configuration is illustrated in Figure 5 and some word-definitions are explained below:

Transmitter: the device, which sends the data to the bus.

Receiver: the device, which receives the data from the bus.

Master: the device, which initiates a transfer, generates clock signals and terminates a transfer.

Slave: the device addressed by a master.

Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message.

Arbitration: the procedure to ensure that, if more than one master tries to control the bus simultaneously, only one is

allowed to do so and the message is not corrupted.

Synchronization: procedure to synchronize the clock signals of two or more devices.

[ ACKNOWLEDGE ]

Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on SDA by the

transmitter during the time when the master generates an extra acknowledge-related clock pulse. A slave receiver which is

addressed must generate an acknowledge-bit, after the reception of each byte. The device that acknowledges must

pull-down the SDA line during the acknowledge-clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge-related clock pulse (set-up and hold times must be taken into consideration). Acknowledgement on the IIC

Interface is illustrated in Figure 6.

Figure 5. System configuration

Figure 4. Definition of START and STOP conditions

Figure 6. Acknowledgement on the 2-line Interface

ST7541 Datasheet(PDF) 17 Page - Sitronix Technology Co., Ltd.