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VG3617801CT Datasheet(PDF) 20 Page - Vanguard International Semiconductor

Part # VG3617801CT
Description  16Mb CMOS Synchronous Dynamic RAM
PDF  68 Pages
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Manufacturer  VML [Vanguard International Semiconductor]
Direct Link  http://www.vis.com.tw
Logo VML - Vanguard International Semiconductor

VG3617801CT Datasheet(HTML) 20 Page - Vanguard International Semiconductor

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Document:1G5-0133
Rev.1
Page 20
VIS
VG3617801CT
16Mb CMOS Synchronous Dynamic RAM
9.READ/WRITE Command Interval
9.1 READ to READ command interval
When a new READ command is asserted during a READ cycle, it will be effective after the CAS latency,
even if the previous READ operation has not completed. READ will be interrupted by another READ.
A READ command can be asserted in every clock without restriction.
READ to READ Command Interval
9.2 WRITE to WRITE Command Interval
When a new WRITE command is asserted during a WRITE cycle, the previous burst will be terminated
and the new burst will begin with the new WRITE command. WRITE will be interrupted by another WRITE.
A WRITE command can be asserted in every clock without restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2
CLK
Command
DQ
QA0
QB2
QB1
QB0
Read A
T0
T1
T2
T3
T4
T5
T6
T7
Hi-Z_
T8
1 cycle
QB3
Read B
Burst lengh=4, CAS latency=2
CLK
Command
DQ
QA0
QB2
QB1
QB0
Write A
T0
T1
T2
T3
T4
T5
T6
T7
Hi-Z_
T8
1 cycle
QB3
Write B



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