VG3617801CT datasheet(15/68 Pages) VML

15 / 68 page

Document:1G5-0133

Rev.1

Page 15

VIS

VG3617801CT

16Mb CMOS Synchronous Dynamic RAM

5.1 Burst Length and Sequence

(Burst of Two)

(Burst of Four)

(Burst of Eight)

Full page burst is an extension of the above tables of sequential addressing, with the length being 512/

256 words for 2Mx8/1Mx16 devices, respectively.

Starting Address

(column address A0, binary)

Sequential Addressing

Sequence (decimal)

Interleave Addressing

Sequence(decimal)

0,1

1,0

Starting Address

(column address A1-A0, binary)

Sequential Addressing

Sequence (decimal)

Interleave Addressing

Sequence(decimal)

0,1,2,3

1,2,3,0

1,0,3,2

2,3,0,1

3,0,1,2

3,2,1,0

Starting Address

(column address A2-A0, binary)

Sequential Addressing

Sequence (decimal)

Interl

eave Addressing

Sequence(decimal)

000

0,1,2,3,4,5,6,7

001

1,2,3,4,5,6,7,0

1,0,3,2,5,4,7,6

010

2,3,4,5,6,7,0,1

2,3,0,1,6,7,4,5

011

3,4,5,6,7,0,1,2

3,2,1,0,7,6,5,4

100

4,5,6,7,0,1,2,3

101

5,6,7,0,1,2,3,4

5,4,7,6,1,0,3,2

110

6,7,0,1,2,3,4,5

6,7,4,5,2,3,0,1

111

7,0,1,2,3,4,5,6

7,6,5,4,3,2,1,0

VG3617801CT Datasheet(PDF) 15 Page - Vanguard International Semiconductor

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