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VG3617801CT Datasheet(PDF) 6 Page - Vanguard International Semiconductor |
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VG3617801CT Datasheet(HTML) 6 Page - Vanguard International Semiconductor |
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6 / 68 page  Document:1G5-0133 Rev.1 Page 6 VIS VG3617801CT 16Mb CMOS Synchronous Dynamic RAM A.C Characteristics: Test Conditions: (Ta=0 to 70°C VDD=3.3V ,VSS=0V) AC input Levels(VIH/VIL) 2.0/0.8V Input timing reference level/ Output timing reference level 1.4V Input rise and fall time 1ns Output load condition 50pF Parameter CAS Latency symbol VG3617801CT Unit -8H -8L -10 Min Max Min Max Min Max CLK cycle time 3 tCk3 10 10 10 ns 2 tCk2 10 13 15 ns CLK to valid output delay 3 tAC3 6 6 8 ns 2 tAC2 6 7 8 ns CLK high pulse width tCH 3 3 4 ns CLK low pulse width tCL 3 3 4 ns CKE setup time tCKS 3 3 3 ns CKE hold time tCKH 1 1 1 ns Address setup time tAS 2 2 3 ns Address hold time tAH 1 1 1 ns Data input setup time tDS 2 2 3 ns Data input hold time tDH 1 1 1 ns Command setup time tCMS 2 2 3 ns Command hold time tCMH 1 1 1 ns Output data hold time tOH 3 3 3 ns CLK to output in low-Z tLZ 0 0 0 ns CLK to output in Hi-Z tHZ 3 8 3 8 3 8 ns Row active to active delay tRRD 20 20 20 ns RAS to CAS delay tRCD 20 20 26 ns Row precharge time tRP 20 20 26 ns ROW active time tRAS 50 120,000 50 120,000 60 120,000 ns ROW cycle time tRC 70 70 86 ns Last data in to burst stop tBDL 1 CLK 1 CLK 1 CLK ns Data-in to ACT(REF) Command (Auto Precharge) tDAL 1CLK+tRP 1CLK+tRP 1CLK+tRP ns Data-in to precharge tDPL 1 CLK 1 CLK 1 CLK ns Transition time tT 1 10 1 10 1 10 ns Mode reg. set cycle tRSC 2 CLK 2 CLK 2 CLK ns Power down exit setup time tPDE 8 8 8 ns Self refresh exit time tSRX 8 8 8 ns Refresh time tREF 32 32 32 ms 0.3V ± |
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