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VG3617801CT Datasheet(PDF) 59 Page - Vanguard International Semiconductor |
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VG3617801CT Datasheet(HTML) 59 Page - Vanguard International Semiconductor |
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59 / 68 page  Document:1G5-0133 Rev.1 Page 59 VIS VG3617801CT 16Mb CMOS Synchronous Dynamic RAM T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Full Page Read Cycle (2 of 2) CLK CKE CS RAS CAS WE A11(BS) A10 A0~A9 DDM DQ t CK3 Burst Length=Full Page, CAS Latency=3 Activate Bank A Command Read Hi-Z Command RAa QAa+1 Bank A The burst counter wraps Burst Stop Read Command Bank B QAa Full page burst operation RAa CAa RBb t RP High Activate Command Bank B RBa RBb CBa QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa0 QBa+1 QBa+2 QBa+3 QBa+4 QBa+5 Activate Command Bank B from the highest order page address back to zero during this time interval Command Precharge Command Bank B does not teminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address RBa |
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