VG3617801CT datasheet(18/68 Pages) VML

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Document:1G5-0133

Rev.1

Page 18

VIS

VG3617801CT

16Mb CMOS Synchronous Dynamic RAM

8.AUTO PRECHARGE

During a READ or WRITE command cycle, A10 controls whether AUTO PRECHARGE is selected. If A10 is

high in the READ or WRITE command (READ with AUTO PRECHARGE command or WRITE with AUTO PRE-

CHARGE command), AUTO PRECHARGE is selected and precharging begins automatically after the burst

access.

In the WRITE cycle, tDAL(min.) must be satisfied to assert the next active command to the bank being pre-

charged.

When using AUTO PRECHARGE in the READ cycle, knowing when the PRECHARGE starts is important

because the tRAS must be satisfied. Once AUTO PRECHARGE has started, an active command to the bank can

be asserted after tRP(min.) has been satisfied.

The timing at which the AUTO PRECHARGE cycle begins depends both on the CAS Iatency programmed

into the mode register and on whether the cycle is READ or WRITE.

8.1 READ with AUTO PRECHARGE

During a READA cycle, the AUTO PRECHARGE begins one clock earlier(CAS Iatency of 2) or two

clocks earlier(CAS Iatency of 3) than the last data word output.

READ with AUTO PRECHARGE

Burst lengh=4

CLK

Command

CAS latency=2

Command

CAS latency=3

Remark READA means READ with AUTO PRECHARGE

Hi-Z

Auto precharge starts

QB0

QB3

QB2

QB1

READA B

Auto precharge starts

Hi-Z

QB0

QB3

QB2

QB1

VG3617801CT Datasheet(PDF) 18 Page - Vanguard International Semiconductor

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