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VG3617801CT Datasheet(PDF) 11 Page - Vanguard International Semiconductor

Part # VG3617801CT
Description  16Mb CMOS Synchronous Dynamic RAM
PDF  68 Pages
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Manufacturer  VML [Vanguard International Semiconductor]
Direct Link  http://www.vis.com.tw
Logo VML - Vanguard International Semiconductor

VG3617801CT Datasheet(HTML) 11 Page - Vanguard International Semiconductor

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Document:1G5-0133
Rev.1
Page 11
VIS
VG3617801CT
16Mb CMOS Synchronous Dynamic RAM
Note 1. All entries assume that CKE was active (High level)during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive(Low level), the device will enter Power down mode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4. If both banks are idle, and CKE is inactive(Low level), the device will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. IIIegal if tRCD is not satisfied.
6. IIIegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data if tDPL is not satisfied.
10. IIIegal if tRRD is not satisfied.
Current state
CS
RAS
CA
WE
Address
Command
Action
Notes
Write
recovering
H
X
X
X
X
DESL
row active after tDPL
L
H
H
H
X
NOP
row active after tDPL
L
H
H
L
X
BST
row active after tDPL
L
H
L
H
BA,CA,A10
READ/READA
Start read, Determine AP
8
L
H
L
L
BA,CA,A10
WRIT/WRITA
New write, Determine AP
L
L
H
H
BA,RA
ACT
ILLEGAL
3
L
L
H
L
BA,A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
PEF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Write
recovering
with auto
precharge
H
X
X
X
X
DESL
precharge after tDPL
L
H
H
H
X
NOP
precharge after tDPL
L
H
H
L
X
BST
precharge after tDPL
L
H
L
H
BA,CA,A10
READ/READA
ILLEGAL
3,8
L
H
L
L
BA,CA,A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA,RA
ACT
ILLEGAL
3
L
L
H
L
BA,A10
REF/PALL
ILLEGAL
3
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Refreshing
H
X
X
X
X
DESL
idle after tRC
L
H
H
X
X
NOP/BST
idle after tRC
L
H
L
X
X
READ/WRIT
ILLEGAL
L
L
H
X
X
ACT/PRE/PALL
ILLEGAL
L
L
L
X
X
REF/SELF/MRS
ILLEGAL
Mode register
accessing
H
X
X
X
X
DESL
idle after 2 Clocks
L
H
H
H
X
NOP
idle after 2 Clocks
L
H
H
L
X
BST
ILLEGAL
L
H
L
X
X
READ/WRITE
ILLEGAL
L
L
X
X
X
ACT/PRE/PALL/
REF/SELF/MRS
ILLEGAL
Nop
Enter
→
Nop
Enter
→
Nop
Enter
→
Nop
Enter
→
Nop
Enter
→
Nop
Enter
→
Nop
Enter
→
Nop
Enter
→
Nop
Enter
→
Nop
Enter
→
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