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VG3617801CT Datasheet(PDF) 25 Page - Vanguard International Semiconductor

Part # VG3617801CT
Description  16Mb CMOS Synchronous Dynamic RAM
PDF  68 Pages
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Manufacturer  VML [Vanguard International Semiconductor]
Direct Link  http://www.vis.com.tw
Logo VML - Vanguard International Semiconductor

VG3617801CT Datasheet(HTML) 25 Page - Vanguard International Semiconductor

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Document:1G5-0133
Rev.1
Page 25
VIS
VG3617801CT
16Mb CMOS Synchronous Dynamic RAM
10.2.2 PRECHARGE TERMINATION in WRITE Cycle
During a WRITE cycle, the BURST WRITE operation can be terminated by a PRECHARGE
command. when the PRECHARGE command is asserted, the BURST WRITE operation in imme-
diately terminated and PRECHARGE starts.
The same bank can be activated again after tRP(min.) from the PRECHARGE command. The
DQM must be high to mask invalid data in.
When CAS latency is 2 or 3, the data written prior to the PRECHARGE command will be cor-
rectly stored. However, invalid data may be written at the same clock as the PRECHARGE com-
mand. To prevent this from happening, DQM must be high at the same clock as the PRECHARGE
command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle33
Burst lengh = X
CLK
Command
CAS latency=2
DQM
Hi-Z
Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
tRP
PRE
ACT
DQ
Write
PRE
ACT
tRP
CAS latency=3
Hi-Z
D0
D3
D2
D1
D0
D3
D2
D1
DQM
D4
D4
command
DQ



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