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VG3617801CT Datasheet(PDF) 49 Page - Vanguard International Semiconductor |
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VG3617801CT Datasheet(HTML) 49 Page - Vanguard International Semiconductor |
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49 / 68 page  Document:1G5-0133 Rev.1 Page 49 VIS VG3617801CT 16Mb CMOS Synchronous Dynamic RAM T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Read and Write Cycle (2 of 2) CLK CKE CS RAS CAS WE A11(BS) A10 A0~A9 DQM DQ t CK3 Burst Length=4, CAS Latency=3 Activate Bank A Command Read Hi-Z Command DAb3 QAc0 QAa0 QAa1 QAa2 QAa3 DAb0 DAb1 Bank A Write Command Bank A QAc3 QAc1 The Read Data The Write Data is Masked with a Zero Clock RAa latency is Masked with Two Clock Latency RAa CAb CAa CAc Read Command Bank A |
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