AD9148BBCZ datasheet(39/73 Pages) AD

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Preliminary Technical Data

AD9148

Rev. PrA | Page 39 of 73

INPUT DATA PORTS

The AD9148 can operate in three data input modes: dual-port

mode, single-port mode, and byte mode. In dual-port mode,

DAC 1 and DAC 2 receive data from Port A, and DAC 3 and

DAC 4 receive data from Port B. In single-port mode, all four

DACs receive data from Port A. In byte mode, all four DACs

receive data from Port A, but the port is split into two 8-bit wide

buses. In all modes, the data input timing is relative to a DCI signal

provided along with the data.

DUAL-PORT MODE

In dual-port mode, the DCI signal indicates to which DAC the

data is intended. On the rising edge of DCI, data is latched into

DAC 1 and DAC 3. On the falling edge of DCI, data is latched

into DAC 2 and DAC 4. This pattern continuously repeats.

There is a SPI programmable option (Register 0x14[6]) to provide

one DCI for both input ports or two DCIs where each DCI is

associated with one input port. Two DCIs are useful when the

data for each port is coming from a different data source. These

cases are illustrated in Figure 45 and Figure 46.

DCIA

A[15:0]

DAC1 DAC2 DAC1 DAC2 DAC1 DAC2 DAC1 DAC2

DAC3 DAC4 DAC3 DAC4 DAC3 DAC4 DAC3 DAC4

B[15:0]

Figure 45. Timing Diagram for Dual-Port Mode, One DCI

DCIA

A[15:0]

DAC1 DAC2 DAC1 DAC2 DAC1 DAC2 DAC1 DAC2

DAC3 DAC4 DAC3 DAC4 DAC3 DAC4 DAC3 DAC4

B[15:0]

DCIB

Figure 46. Timing Diagram for Dual-Port Mode, Two DCI

Each data sample, by default, is expected to be formatted as

MSB sent to Bit 15 and LSB sent to Bit 0 for each port. The

AD9148 contains an option to swap the bus (Register 0x03[4]).

When this bus swap bit is set, the MSB should be sent to Bit 0

and the LSB should be sent to Bit 15 for each port.

SINGLE-PORT MODE

In single-port mode, a FRAME signal must be provided along

with the DCI signal and the data. The FRAME signal indicates

to which DAC the data is intended. When FRAME goes high,

the first data-word goes to DAC 1, and the second data-word

goes to DAC 2. When FRAME goes low, the first data-word

goes to DAC 3, and the second data-word goes to DAC 4. This

pattern continuously repeats as illustrated in Figure 47.

FRAMEA

A[15:0]

DAC1 DAC2 DAC3 DAC4 DAC1 DAC2 DAC3 DAC4

DCIA

Figure 47. Timing Diagram for Single-Port Mode

Each data sample, by default, is expected to be formatted as MSB

sent to Bit 15 and LSB sent to Bit 0. When the bus swap bit is set

(Register 0x03[4]), the MSB should be sent to Bit 0, and the LSB

should be sent to Bit 15 for each port.

The FRAME signal is sampled with the same internal signal as

the data and has the same set-up and hold timing relative to DCI. If

desired, only the first FRAME pulse needs to be generated. This

initializes the internal clock phases inside the device, and data

latches just as if the periodic FRAME signal were sent.

AD9148BBCZ Datasheet(PDF) 39 Page - Analog Devices

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