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AD9148BBCZ Datasheet(PDF) 23 Page - Analog Devices |
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AD9148BBCZ Datasheet(HTML) 23 Page - Analog Devices |
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23 / 73 page  Preliminary Technical Data AD9148 Rev. PrA | Page 23 of 73 SPI REGISTER MAP Table 12. Register Map Addr Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x00 Comm SDIO direction LSB/ MSB first Software reset DAC SPI select 0x00 0x01 Power control Power- Down DAC Set 1 Power- Down DAC Set 2 Power- Down Data Receiver 0x00 0x03 Data format Binary format Q first enable Dual-port mode Bus swap Byte mode Byte swap 0x20 0x04 Interrupt Enable 0 Enable PLL lock lost Enable PLL lock Enable sync lock lost Enable sync lock Enable FIFO SPI aligned Enable FIFO Warning 1 Enable FIFO Warning 2 0x00 0x05 Interrupt Enable 1 Enable AED compare pass Enable AED compare fail Enable SED compare fail 0x00 0x06 Event Flag 0 PLL lock lost PLL lock Sync lock lost Sync lock FIFO SPI aligned FIFO Warning 1 FIFO Warning 2 0x07 Event Flag 1 AED compare pass AED compare fail SED compare fail 0x08 Clock receiver control CLK duty correction REFCLK duty correction CLK cross correction REFCLK cross correction 0 1 1 1 0x37 0x0A PLL Control 0 PLL enable PLL manual enable Manual VCO Band[5:0] 0x40 0x0C PLL Control 1 PLL Loop Bandwidth[2:0] 0 1 0 0 1 0xF1 0x0D PLL Control 2 N2[1:0] PLL cross control enable N0[1:0] N1[1:0] 0xD9 0x0E PLL Status 0 PLL Control Voltage[3:0] 0x0F PLL Status 1 VCO Band Readback[5:0] 0x10 Sync Control 0 Sync enable FIFO rate/ data rate toggle Rising edge sync Sync Averaging[2:0] 0x08 0x11 Sync Control 1 Sync Phase Request[5:0] 0x00 0x12 Sync Status 0 Sync lost Sync locked 0x14 Data receiver control One DCI 0x00 0x15 Data receiver status LVDS rcvr frame high LVDS rcvr frame low LVDS rcvr DCI high LVDS rcvr DCI low LVDS rcvr Port B high LVDS rcvr Port B low LVDS rcvr Port A high LVDS rcvr Port A low 0x17 FIFO Status/ Control Port A FIFO Warning 1 FIFO Warning 2 FIFO reset aligned FIFO SPI align ack FIFO SPI align requesting FIFO Phase Offset[2:0] 0x00 0x18 FIFO Status Port A FIFO Level[7:0] 0x19 FIFO Status/ Control Port B FIFO Warning 1 FIFO Warning 2 FIFO reset aligned FIFO SPI align ack FIFO SPI align requesting FIFO Phase Offset[2:0] 0x00 0x1A FIFO Status Port B FIFO Level[7:0] 0x1C HB1 control Enable pre mod Bypass sinc−1 HB1[1:0] Bypass HB1 0x40 0x1D HB2 control HB2[2:0] Bypass HB2 0x00 0x1E HB3 control Bypass phase adj HB3[2:0] Bypass HB3 0x81 0x1F CHIP ID Chip ID[7:0] 0x20 |
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