AD9148BBCZ datasheet(21/73 Pages) AD

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Preliminary Technical Data

AD9148

Rev. PrA | Page 21 of 73

SERIAL PERIPHERAL INTERFACE

SDO

SPI

PORT

SDIO

SCLK

CSB

Figure 40. SPI Por

The serial port is a flexible, synchronous serial communications

port allowing easy interface to many industry-standard micro-

controllers and microprocessors. The serial I/O is compatible

with most synchronous transfer formats, including both the

Motorola SPI and Intel

® SSR protocols. The interface allows

read/write access to all registers that configure the AD9148.

Single- or multiple-byte transfers are supported, as well as MSB-

first or LSB-first transfer formats. The serial interface ports can

be configured as a single pin I/O (SDIO) or two unidirectional

pins for input/output (SDIO/SDO).

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to a communication cycle with the AD9148.

Phase 1 is the instruction cycle (the writing of an instruction

byte into the device), coincident with the first eight SCLK rising

edges. The instruction byte provides the serial port controller

with information regarding the data transfer cycle, Phase 2 of

the communication cycle. The Phase 1 instruction byte defines

whether the upcoming data transfer is a read or write and the

starting register address for the first byte of the data transfer.

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the device.

A logic high on the CSB pin followed by a logic low resets the

SPI port timing to the initial state of the instruction cycle. From

this state, the next eight rising SCLK edges represent the instruction

bits of the current I/O operation, regardless of the state of the

internal registers or the other signal levels at the inputs to the

SPI port. If the SPI port is in an instruction cycle or a data

transfer cycle, none of the present data is written.

The remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the device and

the system controller. Phase 2 of the communication cycle is a

transfer of one or more data bytes. Registers change immediately

upon writing to the last bit of each transfer byte.

DATA FORMAT

The instruction byte contains the information shown in Table 11.

Table 11. SPI Instruction Byte

I7 (MSB)

I0 (LSB)

R/W

R/W, Bit 7 of the instruction byte, determines whether a read or

a write data transfer occurs after the instruction byte write.

Logic high indicates a read operation, and Logic 0 indicates a

write operation.

A6 through A0—Bit 6 through Bit 0 of the instruction byte

determine the register that is accessed during the data transfer

portion of the communication cycle. For multibyte transfers, this

address is the starting byte address. The remaining register

addresses are generated by the device based on the LSB-first bit

(Register 0x00, Bit 6).

SPI PIN DESCRIPTIONS

Serial Clock (SCLK)

The serial clock pin synchronizes data to and from the device

and runs the internal state machines. The maximum frequency

of SCLK is 40 MHz. All data input is registered on the rising

edge of SCLK. All data is driven out on the falling edge of SCLK.

Chip Select (CSB)

Active low input starts and gates a communication cycle. It

allows more than one device to be used on the same serial

communications lines. The SDO and SDIO pins go to a high

impedance state when this input is high. Chip select should stay

low during the entire communication cycle.

Serial Data I/O (SDIO)

Data is always written into the device on this pin. However, this

pin can be used as a bidirectional data line. The configuration

of this pin is controlled by Register 0x00, Bit 7. The default is

Logic 0, configuring the SDIO pin as unidirectional.

Serial Data Out (SDO)

Data is read from this pin for protocols that use separate lines

for transmitting and receiving data. In the case where the device

operates in a single bidirectional I/O mode, this pin does not

output data and is set to a high impedance state.

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