AD9148BBCZ datasheet(5/73 Pages) AD

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Preliminary Technical Data

AD9148

Rev. PrA | Page 5 of 73

INPUT/OUTPUT SIGNAL SPECIFICATIONS

TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless

otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

CMOS INPUT LOGIC LEVEL (SCLK, SDIO, CSB, RESETE, TMS, TDI, TCK)

Input VIN Logic High (IOVDD = 1.8 V)

1.2

Input VIN Logic High (IOVDD = 3.3 V)

2.0

Input VIN Logic Low (IOVDD = 1.8 V)

0.6

Input VIN Logic Low (IOVDD = 3.3 V)

0.8

CMOS OUTPUT LOGIC LEVEL (SDIO, SDO, IRQE, PLL_LOCK, TDO)

Output VOUT Logic High (IOVDD = 1.8 V)

1.4

Output VOUT Logic High (IOVDD = 3.3 V)

2.4

Output VOUT Logic Low (IOVDD = 1.8 V)

0.4

Output VOUT Logic Low (IOVDD = 3.3 V)

0.4

LVDS RECEIVER INPUTS (A[15:0]_x, B[15:0]_x, DCIA_x, DCIB_x, FRAMEA_x, FRAMEB_x)

Input Voltage Range, VIA or VIB

825

1575

Input Differential Threshold, VIDTH

−100

+100

Input Differential Hysteresis, VIDTHH to VIDTHL

Receiver Differential Input Impedance, RIN

120

LVDS Input Rate, fINTERFACE (See Table 4)

1200

MSPS

DAC CLOCK INPUT (CLK_P, CLK_N)

Differential Peak-to-Peak Voltage

100

500

2000

Common-Mode Voltage (Self-Biasing, AC-Coupled)

1.25

Maximum Clock Rate

1000

MSPS

REFERENCE CLOCK INPUT (REFCLK_P/SYNC_P AND REFCLK_N/SYNC_N)

Differential Peak-to-Peak Voltage

100

500

2000

Common-Mode Voltage (Self-Biasing, AC-Coupled)

1.25

Maximum Clock Rate

500

MSPS

Minimum Clock Rate (PLL Enabled)

Loop Divider = /2

125

MSPS

Loop Divider = /4

62.5

MSPS

Loop Divider = /8

31.25

MSPS

Loop Divider = /16

15.625

MSPS

SERIAL PERIPHERAL INTERFACE

Maximum Clock Rate (SCLK)

MHz

Minimum Pulse Width High (tPWH)

12.5

Minimum Pulse Width Low (tPWL)

12.5

Set-Up Time, SDI to SCLK (tDS)

1.9

Hold Time, SDI to SCLK (tDH)

0.2

Data Valid, SDO to SCLK (tDV)

Setup time, CSB to SCLK (tDCSB)

1.4

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