AD9148BBCZ datasheet(49/73 Pages) AD

49 / 73 page

Preliminary Technical Data

AD9148

Rev. PrA | Page 49 of 73

INTERFACE TIMING

The timing diagram for the digital interface port is shown in

Figure 58. The sampling point of the data bus nominally occurs

TBD ps after each edge of the DCI signal and has an uncertainty of

± TBD ps, as illustrated by the sampling interval. The data and

FRAME signals must be valid throughout this sampling interval.

The data and FRAME signals may change at any time between

sampling intervals.

The setup (tS) and hold (tH) times with respect to the edges are

shown in Figure 58. The minimum setup and hold times are

shown in Table 15.

Table 15. Data Port Setup and Hold Times

DCI Delay

(Register 0x72[1:0])

Minimum Setup

Time, tS (ns)

Minimum Hold

Time, tH (ns)

TBD

The data interface timing can be verified by using the SED

circuitry. See the Interface Timing Validation section for details.

In data rate mode with synchronization enabled, a second timing

constraint between DCI and DACCLK must be met in addition

to the DCI-to-data timing shown in Table 16. In data rate mode,

only one FIFO slot is being used. The DCI to DACCLK timing

restriction is required to prevent data being written to and read

from the FIFO slot at the same time. The required timing

between DCI and DACCLK is shown in Figure 57.

DCI

DACCLK/

REFCLK

tDATA

tSDCI

tHDCI

SAMPLING

INTERVAL

Figure 57. Timing Diagram for Input Data Port (Data Rate Mode with Sync On)

Table 16. DCI to DACCLK Setup and Hold Times vs. DCI

Delay Value

DCI Delay

(Register 0x72[1:0])

Minimum Setup

Time, tSDCI (ns)

Minimum Hold

Time, tHDCI (ns)

TBD

tDATA

SAMPLING

INTERVAL

SAMPLING

INTERVAL

Figure 58. Timing Diagram for Input Data Ports

AD9148BBCZ Datasheet(PDF) 49 Page - Analog Devices

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